From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: matthew.brost@intel.com, tvrtko.ursulin@intel.com, daniele.ceraolospurio@intel.com, jason.ekstrand@intel.com, jon.bloomfield@intel.com, daniel.vetter@intel.com, john.c.harrison@intel.com Subject: [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Date: Thu, 6 May 2021 12:14:38 -0700 [thread overview] Message-ID: <20210506191451.77768-85-matthew.brost@intel.com> (raw) In-Reply-To: <20210506191451.77768-1-matthew.brost@intel.com> Add a heuristic which checks if over half of the available guc_ids are currently consumed by requests not ready to be submitted. If this heuristic is true at request creation time (normal guc_id allocation location) force all submissions + guc_ids allocations to tasklet. Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/intel_context_types.h | 3 ++ drivers/gpu/drm/i915/gt/intel_reset.c | 9 ++++ drivers/gpu/drm/i915/gt/uc/intel_guc.h | 1 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 53 +++++++++++++++++-- .../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 + 5 files changed, 65 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index a25ea8fe2029..998f3839411a 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -186,6 +186,9 @@ struct intel_context { /* GuC lrc descriptor reference count */ atomic_t guc_id_ref; + /* GuC number of requests not ready */ + atomic_t guc_num_rq_not_ready; + /* * GuC ID link - in list when unpinned but guc_id still valid in GuC */ diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 4347cc2dcea0..be25e39f0dd8 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -22,6 +22,7 @@ #include "intel_reset.h" #include "uc/intel_guc.h" +#include "uc/intel_guc_submission.h" #define RESET_MAX_RETRIES 3 @@ -776,6 +777,14 @@ static void nop_submit_request(struct i915_request *request) { RQ_TRACE(request, "-EIO\n"); + /* + * XXX: Kinda ugly to check for GuC submission here but this function is + * going away once we switch to the DRM scheduler so we can live with + * this for now. + */ + if (intel_engine_uses_guc(request->engine)) + intel_guc_decr_num_rq_not_ready(request->context); + request = i915_request_mark_eio(request); if (request) { i915_request_submit(request); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index bd477209839b..26a0225f45e9 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -76,6 +76,7 @@ struct intel_guc { struct ida guc_ids; u32 num_guc_ids; u32 max_guc_ids; + atomic_t num_guc_ids_not_ready; struct list_head guc_id_list_no_ref; struct list_head guc_id_list_unpinned; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 037a7ee4971b..aa5e608deed5 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1323,6 +1323,41 @@ static inline void queue_request(struct i915_sched_engine *sched_engine, kick_tasklet(&rq->engine->gt->uc.guc); } +/* Macro to tweak heuristic, using a simple over 50% not ready for now */ +#define TOO_MANY_GUC_IDS_NOT_READY(avail, consumed) \ + (consumed > avail / 2) +static bool too_many_guc_ids_not_ready(struct intel_guc *guc, + struct intel_context *ce) +{ + u32 available_guc_ids, guc_ids_consumed; + + available_guc_ids = guc->num_guc_ids; + guc_ids_consumed = atomic_read(&guc->num_guc_ids_not_ready); + + if (TOO_MANY_GUC_IDS_NOT_READY(available_guc_ids, guc_ids_consumed)) { + set_and_update_guc_ids_exhausted(guc); + return true; + } + + return false; +} + +static void incr_num_rq_not_ready(struct intel_context *ce) +{ + struct intel_guc *guc = ce_to_guc(ce); + + if (!atomic_fetch_add(1, &ce->guc_num_rq_not_ready)) + atomic_inc(&guc->num_guc_ids_not_ready); +} + +void intel_guc_decr_num_rq_not_ready(struct intel_context *ce) +{ + struct intel_guc *guc = ce_to_guc(ce); + + if (atomic_fetch_add(-1, &ce->guc_num_rq_not_ready) == 1) + atomic_dec(&guc->num_guc_ids_not_ready); +} + static bool need_tasklet(struct intel_guc *guc, struct intel_context *ce) { struct i915_sched_engine * const sched_engine = @@ -1369,6 +1404,8 @@ static void guc_submit_request(struct i915_request *rq) kick_tasklet(guc); spin_unlock_irqrestore(&sched_engine->lock, flags); + + intel_guc_decr_num_rq_not_ready(rq->context); } #define GUC_ID_START 64 /* First 64 guc_ids reserved */ @@ -2240,10 +2277,13 @@ static int guc_request_alloc(struct i915_request *rq) GEM_BUG_ON(!intel_context_is_pinned(rq->context)); /* - * guc_ids are exhausted, don't allocate one here, defer to submission - * in the tasklet. + * guc_ids are exhausted or a heuristic is met indicating too many + * guc_ids are waiting on requests with submission dependencies (not + * ready to submit). Don't allocate one here, defer to submission in the + * tasklet. */ - if (test_and_update_guc_ids_exhausted(guc)) { + if (test_and_update_guc_ids_exhausted(guc) || + too_many_guc_ids_not_ready(guc, ce)) { set_bit(I915_FENCE_FLAG_GUC_ID_NOT_PINNED, &rq->fence.flags); goto out; } @@ -2299,6 +2339,7 @@ static int guc_request_alloc(struct i915_request *rq) */ set_bit(I915_FENCE_FLAG_GUC_ID_NOT_PINNED, &rq->fence.flags); set_and_update_guc_ids_exhausted(guc); + incr_num_rq_not_ready(ce); return 0; } else if (unlikely(ret < 0)) { @@ -2321,6 +2362,8 @@ static int guc_request_alloc(struct i915_request *rq) clear_bit(CONTEXT_LRCA_DIRTY, &ce->flags); out: + incr_num_rq_not_ready(ce); + /* * We block all requests on this context if a G2H is pending for a * schedule disable or context deregistration as the GuC will fail a @@ -3088,6 +3131,8 @@ void intel_guc_log_submission_info(struct intel_guc *guc, drm_printf(p, "GuC submit flags: 0x%04lx\n", guc->flags); drm_printf(p, "GuC total number request without guc_id: %d\n", guc->total_num_rq_with_no_guc_id); + drm_printf(p, "GuC Number GuC IDs not ready: %d\n", + atomic_read(&guc->num_guc_ids_not_ready)); drm_printf(p, "GuC stall reason: %d\n", guc->submission_stall_reason); drm_printf(p, "GuC stalled request: %s\n", yesno(guc->stalled_rq)); @@ -3127,6 +3172,8 @@ void intel_guc_log_context_info(struct intel_guc *guc, atomic_read(&ce->pin_count)); drm_printf(p, "\t\tGuC ID Ref Count: %u\n", atomic_read(&ce->guc_id_ref)); + drm_printf(p, "\t\tNumber Requests Not Ready: %u\n", + atomic_read(&ce->guc_num_rq_not_ready)); drm_printf(p, "\t\tSchedule State: 0x%x, 0x%x\n\n", ce->guc_state.sched_state, atomic_read(&ce->guc_sched_state_no_lock)); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h index a2a3fad72be1..60c8b9aaad6e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h @@ -51,4 +51,6 @@ static inline bool intel_guc_submission_is_used(struct intel_guc *guc) return intel_guc_is_used(guc) && intel_guc_submission_is_wanted(guc); } +void intel_guc_decr_num_rq_not_ready(struct intel_context *ce); + #endif -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: jason.ekstrand@intel.com, daniel.vetter@intel.com Subject: [Intel-gfx] [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Date: Thu, 6 May 2021 12:14:38 -0700 [thread overview] Message-ID: <20210506191451.77768-85-matthew.brost@intel.com> (raw) In-Reply-To: <20210506191451.77768-1-matthew.brost@intel.com> Add a heuristic which checks if over half of the available guc_ids are currently consumed by requests not ready to be submitted. If this heuristic is true at request creation time (normal guc_id allocation location) force all submissions + guc_ids allocations to tasklet. Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/intel_context_types.h | 3 ++ drivers/gpu/drm/i915/gt/intel_reset.c | 9 ++++ drivers/gpu/drm/i915/gt/uc/intel_guc.h | 1 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 53 +++++++++++++++++-- .../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 + 5 files changed, 65 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index a25ea8fe2029..998f3839411a 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -186,6 +186,9 @@ struct intel_context { /* GuC lrc descriptor reference count */ atomic_t guc_id_ref; + /* GuC number of requests not ready */ + atomic_t guc_num_rq_not_ready; + /* * GuC ID link - in list when unpinned but guc_id still valid in GuC */ diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 4347cc2dcea0..be25e39f0dd8 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -22,6 +22,7 @@ #include "intel_reset.h" #include "uc/intel_guc.h" +#include "uc/intel_guc_submission.h" #define RESET_MAX_RETRIES 3 @@ -776,6 +777,14 @@ static void nop_submit_request(struct i915_request *request) { RQ_TRACE(request, "-EIO\n"); + /* + * XXX: Kinda ugly to check for GuC submission here but this function is + * going away once we switch to the DRM scheduler so we can live with + * this for now. + */ + if (intel_engine_uses_guc(request->engine)) + intel_guc_decr_num_rq_not_ready(request->context); + request = i915_request_mark_eio(request); if (request) { i915_request_submit(request); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index bd477209839b..26a0225f45e9 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -76,6 +76,7 @@ struct intel_guc { struct ida guc_ids; u32 num_guc_ids; u32 max_guc_ids; + atomic_t num_guc_ids_not_ready; struct list_head guc_id_list_no_ref; struct list_head guc_id_list_unpinned; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 037a7ee4971b..aa5e608deed5 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1323,6 +1323,41 @@ static inline void queue_request(struct i915_sched_engine *sched_engine, kick_tasklet(&rq->engine->gt->uc.guc); } +/* Macro to tweak heuristic, using a simple over 50% not ready for now */ +#define TOO_MANY_GUC_IDS_NOT_READY(avail, consumed) \ + (consumed > avail / 2) +static bool too_many_guc_ids_not_ready(struct intel_guc *guc, + struct intel_context *ce) +{ + u32 available_guc_ids, guc_ids_consumed; + + available_guc_ids = guc->num_guc_ids; + guc_ids_consumed = atomic_read(&guc->num_guc_ids_not_ready); + + if (TOO_MANY_GUC_IDS_NOT_READY(available_guc_ids, guc_ids_consumed)) { + set_and_update_guc_ids_exhausted(guc); + return true; + } + + return false; +} + +static void incr_num_rq_not_ready(struct intel_context *ce) +{ + struct intel_guc *guc = ce_to_guc(ce); + + if (!atomic_fetch_add(1, &ce->guc_num_rq_not_ready)) + atomic_inc(&guc->num_guc_ids_not_ready); +} + +void intel_guc_decr_num_rq_not_ready(struct intel_context *ce) +{ + struct intel_guc *guc = ce_to_guc(ce); + + if (atomic_fetch_add(-1, &ce->guc_num_rq_not_ready) == 1) + atomic_dec(&guc->num_guc_ids_not_ready); +} + static bool need_tasklet(struct intel_guc *guc, struct intel_context *ce) { struct i915_sched_engine * const sched_engine = @@ -1369,6 +1404,8 @@ static void guc_submit_request(struct i915_request *rq) kick_tasklet(guc); spin_unlock_irqrestore(&sched_engine->lock, flags); + + intel_guc_decr_num_rq_not_ready(rq->context); } #define GUC_ID_START 64 /* First 64 guc_ids reserved */ @@ -2240,10 +2277,13 @@ static int guc_request_alloc(struct i915_request *rq) GEM_BUG_ON(!intel_context_is_pinned(rq->context)); /* - * guc_ids are exhausted, don't allocate one here, defer to submission - * in the tasklet. + * guc_ids are exhausted or a heuristic is met indicating too many + * guc_ids are waiting on requests with submission dependencies (not + * ready to submit). Don't allocate one here, defer to submission in the + * tasklet. */ - if (test_and_update_guc_ids_exhausted(guc)) { + if (test_and_update_guc_ids_exhausted(guc) || + too_many_guc_ids_not_ready(guc, ce)) { set_bit(I915_FENCE_FLAG_GUC_ID_NOT_PINNED, &rq->fence.flags); goto out; } @@ -2299,6 +2339,7 @@ static int guc_request_alloc(struct i915_request *rq) */ set_bit(I915_FENCE_FLAG_GUC_ID_NOT_PINNED, &rq->fence.flags); set_and_update_guc_ids_exhausted(guc); + incr_num_rq_not_ready(ce); return 0; } else if (unlikely(ret < 0)) { @@ -2321,6 +2362,8 @@ static int guc_request_alloc(struct i915_request *rq) clear_bit(CONTEXT_LRCA_DIRTY, &ce->flags); out: + incr_num_rq_not_ready(ce); + /* * We block all requests on this context if a G2H is pending for a * schedule disable or context deregistration as the GuC will fail a @@ -3088,6 +3131,8 @@ void intel_guc_log_submission_info(struct intel_guc *guc, drm_printf(p, "GuC submit flags: 0x%04lx\n", guc->flags); drm_printf(p, "GuC total number request without guc_id: %d\n", guc->total_num_rq_with_no_guc_id); + drm_printf(p, "GuC Number GuC IDs not ready: %d\n", + atomic_read(&guc->num_guc_ids_not_ready)); drm_printf(p, "GuC stall reason: %d\n", guc->submission_stall_reason); drm_printf(p, "GuC stalled request: %s\n", yesno(guc->stalled_rq)); @@ -3127,6 +3172,8 @@ void intel_guc_log_context_info(struct intel_guc *guc, atomic_read(&ce->pin_count)); drm_printf(p, "\t\tGuC ID Ref Count: %u\n", atomic_read(&ce->guc_id_ref)); + drm_printf(p, "\t\tNumber Requests Not Ready: %u\n", + atomic_read(&ce->guc_num_rq_not_ready)); drm_printf(p, "\t\tSchedule State: 0x%x, 0x%x\n\n", ce->guc_state.sched_state, atomic_read(&ce->guc_sched_state_no_lock)); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h index a2a3fad72be1..60c8b9aaad6e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h @@ -51,4 +51,6 @@ static inline bool intel_guc_submission_is_used(struct intel_guc *guc) return intel_guc_is_used(guc) && intel_guc_submission_is_wanted(guc); } +void intel_guc_decr_num_rq_not_ready(struct intel_context *ce); + #endif -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-05-06 19:00 UTC|newest] Thread overview: 504+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-06 19:13 [RFC PATCH 00/97] Basic GuC submission support in the i915 Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork 2021-05-06 19:13 ` [RFC PATCH 01/97] drm/i915/gt: Move engine setup out of set_default_submission Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 0:25 ` Matthew Brost 2021-05-19 0:25 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 02/97] drm/i915/gt: Move submission_method into intel_gt Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 3:10 ` Matthew Brost 2021-05-19 3:10 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 03/97] drm/i915/gt: Move CS interrupt handler to the backend Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 3:31 ` Matthew Brost 2021-05-19 3:31 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:45 ` Tvrtko Ursulin 2021-05-25 8:45 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 04/97] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-20 16:47 ` Matthew Brost 2021-05-20 16:47 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 05/97] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 10:30 ` Michal Wajdeczko 2021-05-24 10:30 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 0:31 ` Matthew Brost 2021-05-25 0:31 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 07/97] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 10:48 ` Michal Wajdeczko 2021-05-24 10:48 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 0:36 ` Matthew Brost 2021-05-25 0:36 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 08/97] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 23:52 ` Michał Winiarski 2021-05-24 23:52 ` [Intel-gfx] " Michał Winiarski 2021-05-06 19:13 ` [RFC PATCH 09/97] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:38 ` Matthew Brost 2021-05-25 2:38 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 10/97] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 0:42 ` Matthew Brost 2021-05-25 0:42 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 11/97] drm/i915/guc: Only rely on own CTB size Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:47 ` Matthew Brost 2021-05-25 2:47 ` [Intel-gfx] " Matthew Brost 2021-05-25 12:48 ` Michal Wajdeczko 2021-05-25 12:48 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 12/97] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:53 ` Matthew Brost 2021-05-25 2:53 ` [Intel-gfx] " Matthew Brost 2021-05-25 13:07 ` Michal Wajdeczko 2021-05-25 13:07 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 16:56 ` Matthew Brost 2021-05-25 16:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 13/97] drm/i915/guc: Replace CTB array with explicit members Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 3:15 ` Matthew Brost 2021-05-25 3:15 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 14/97] drm/i915/guc: Update sizes of CTB buffers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:56 ` Matthew Brost 2021-05-25 2:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 15/97] drm/i915/guc: Relax CTB response timeout Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:08 ` Matthew Brost 2021-05-25 18:08 ` [Intel-gfx] " Matthew Brost 2021-05-25 19:37 ` Michal Wajdeczko 2021-05-25 19:37 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 3:21 ` Matthew Brost 2021-05-25 3:21 ` [Intel-gfx] " Matthew Brost 2021-05-25 13:10 ` Michal Wajdeczko 2021-05-25 3:21 ` Matthew Brost 2021-05-25 3:21 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 17/97] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 16:14 ` Matthew Brost 2021-05-25 16:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 18/97] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:15 ` Matthew Brost 2021-05-25 18:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 19:43 ` Michal Wajdeczko 2021-05-25 19:43 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 19/97] drm/i915/guc: Always copy CT message to new allocation Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:25 ` Matthew Brost 2021-05-25 18:25 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 20/97] drm/i915/guc: Introduce unified HXG messages Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:16 ` Daniel Vetter 2021-05-11 15:16 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:59 ` Matthew Brost 2021-05-11 17:59 ` [Intel-gfx] " Matthew Brost 2021-05-11 22:11 ` Michal Wajdeczko 2021-05-11 22:11 ` [Intel-gfx] " Michal Wajdeczko 2021-05-12 8:40 ` Daniel Vetter 2021-05-12 8:40 ` [Intel-gfx] " Daniel Vetter 2021-05-06 19:13 ` [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 22/97] drm/i915/guc: Update CTB response status Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 23/97] drm/i915/guc: Support per context scheduling policies Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 1:15 ` Matthew Brost 2021-05-25 1:15 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 24/97] drm/i915/guc: Add flag for mark broken CTB Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-27 19:44 ` Matthew Brost 2021-05-27 19:44 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 25/97] drm/i915/guc: New definition of the CTB descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 26/97] drm/i915/guc: New definition of the CTB registration action Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 27/97] drm/i915/guc: New CTB based communication Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 28/97] drm/i915/guc: Kill guc_clients.ct_pool Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 1:01 ` Matthew Brost 2021-05-25 1:01 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 29/97] drm/i915/guc: Update firmware to v60.1.2 Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 30/97] drm/i915/uc: turn on GuC/HuC auto mode by default Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 11:00 ` Michal Wajdeczko 2021-05-24 11:00 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 31/97] drm/i915/guc: Early initialization of GuC send registers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-26 20:28 ` Matthew Brost 2021-05-26 20:28 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 32/97] drm/i915: Introduce i915_sched_engine object Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:18 ` Daniel Vetter 2021-05-11 15:18 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:56 ` Matthew Brost 2021-05-11 17:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 33/97] drm/i915: Engine relative MMIO Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:05 ` Tvrtko Ursulin 2021-05-25 9:05 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 34/97] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-26 20:41 ` Matthew Brost 2021-05-26 20:41 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 35/97] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 11:59 ` Michal Wajdeczko 2021-05-24 11:59 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:32 ` Matthew Brost 2021-05-25 17:32 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 36/97] drm/i915/guc: Add non blocking CTB send function Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 12:21 ` Michal Wajdeczko 2021-05-24 12:21 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:30 ` Matthew Brost 2021-05-25 17:30 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:21 ` Tvrtko Ursulin 2021-05-25 9:21 ` Tvrtko Ursulin 2021-05-25 17:21 ` Matthew Brost 2021-05-25 17:21 ` Matthew Brost 2021-05-26 8:57 ` Tvrtko Ursulin 2021-05-26 8:57 ` Tvrtko Ursulin 2021-05-26 18:10 ` Matthew Brost 2021-05-26 18:10 ` Matthew Brost 2021-05-27 10:02 ` Tvrtko Ursulin 2021-05-27 10:02 ` Tvrtko Ursulin 2021-05-27 14:35 ` Matthew Brost 2021-05-27 14:35 ` Matthew Brost 2021-05-27 15:11 ` Tvrtko Ursulin 2021-05-27 15:11 ` Tvrtko Ursulin 2021-06-07 17:31 ` Matthew Brost 2021-06-07 17:31 ` Matthew Brost 2021-06-08 8:39 ` Tvrtko Ursulin 2021-06-08 8:39 ` Tvrtko Ursulin 2021-06-08 8:46 ` Daniel Vetter 2021-06-08 8:46 ` Daniel Vetter 2021-06-09 23:10 ` Matthew Brost 2021-06-09 23:10 ` Matthew Brost 2021-06-10 15:27 ` Daniel Vetter 2021-06-10 15:27 ` Daniel Vetter 2021-06-24 16:38 ` Matthew Brost 2021-06-24 16:38 ` Matthew Brost 2021-06-24 17:25 ` Daniel Vetter 2021-06-24 17:25 ` Daniel Vetter 2021-06-09 13:58 ` Michal Wajdeczko 2021-06-09 13:58 ` Michal Wajdeczko 2021-06-09 23:05 ` Matthew Brost 2021-06-09 23:05 ` Matthew Brost 2021-06-09 14:14 ` Michal Wajdeczko 2021-06-09 14:14 ` Michal Wajdeczko 2021-06-09 23:13 ` Matthew Brost 2021-06-09 23:13 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 37/97] drm/i915/guc: Add stall timer to " Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 12:58 ` Michal Wajdeczko 2021-05-24 12:58 ` [Intel-gfx] " Michal Wajdeczko 2021-05-24 18:35 ` Matthew Brost 2021-05-24 18:35 ` [Intel-gfx] " Matthew Brost 2021-05-25 14:15 ` Michal Wajdeczko 2021-05-25 14:15 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 16:54 ` Matthew Brost 2021-05-25 16:54 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 38/97] drm/i915/guc: Optimize CTB writes and reads Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:31 ` Michal Wajdeczko 2021-05-24 13:31 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:39 ` Matthew Brost 2021-05-25 17:39 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 39/97] drm/i915/guc: Increase size of CTB buffers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:43 ` Michal Wajdeczko 2021-05-24 13:43 ` Michal Wajdeczko 2021-05-24 18:40 ` Matthew Brost 2021-05-24 18:40 ` Matthew Brost 2021-05-25 9:24 ` Tvrtko Ursulin 2021-05-25 9:24 ` Tvrtko Ursulin 2021-05-25 17:15 ` Matthew Brost 2021-05-25 17:15 ` Matthew Brost 2021-05-26 9:30 ` Tvrtko Ursulin 2021-05-26 9:30 ` Tvrtko Ursulin 2021-05-26 18:20 ` Matthew Brost 2021-05-26 18:20 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 40/97] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:45 ` Michal Wajdeczko 2021-05-24 13:45 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 41/97] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 42/97] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 43/97] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:26 ` Daniel Vetter 2021-05-11 15:26 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:01 ` Matthew Brost 2021-05-11 17:01 ` [Intel-gfx] " Matthew Brost 2021-05-11 17:43 ` Daniel Vetter 2021-05-11 17:43 ` [Intel-gfx] " Daniel Vetter 2021-05-11 19:34 ` Matthew Brost 2021-05-11 19:34 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 44/97] drm/i915/guc: Implement GuC submission tasklet Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:43 ` Tvrtko Ursulin 2021-05-25 9:43 ` Tvrtko Ursulin 2021-05-25 17:10 ` Matthew Brost 2021-05-25 17:10 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 45/97] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 46/97] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-29 20:32 ` Michal Wajdeczko 2021-05-29 20:32 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:14 ` [RFC PATCH 47/97] drm/i915/guc: Insert fence on context when deregistering Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 48/97] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 49/97] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:37 ` Daniel Vetter 2021-05-11 15:37 ` [Intel-gfx] " Daniel Vetter 2021-05-11 16:31 ` Matthew Brost 2021-05-11 16:31 ` [Intel-gfx] " Matthew Brost 2021-05-26 10:26 ` Tvrtko Ursulin 2021-05-26 10:26 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 50/97] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 51/97] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 52/97] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 53/97] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:52 ` Tvrtko Ursulin 2021-05-25 9:52 ` Tvrtko Ursulin 2021-05-25 17:01 ` Matthew Brost 2021-05-25 17:01 ` Matthew Brost 2021-05-26 9:25 ` Tvrtko Ursulin 2021-05-26 9:25 ` Tvrtko Ursulin 2021-05-26 18:15 ` Matthew Brost 2021-05-26 18:15 ` Matthew Brost 2021-05-27 8:41 ` Tvrtko Ursulin 2021-05-27 8:41 ` Tvrtko Ursulin 2021-05-27 14:38 ` Matthew Brost 2021-05-27 14:38 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 54/97] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 55/97] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-07 5:56 ` kernel test robot 2021-05-25 10:06 ` Tvrtko Ursulin 2021-05-25 10:06 ` Tvrtko Ursulin 2021-05-25 17:07 ` Matthew Brost 2021-05-25 17:07 ` Matthew Brost 2021-05-26 9:21 ` Tvrtko Ursulin 2021-05-26 9:21 ` Tvrtko Ursulin 2021-05-26 18:18 ` Matthew Brost 2021-05-26 18:18 ` Matthew Brost 2021-05-27 9:02 ` Tvrtko Ursulin 2021-05-27 9:02 ` Tvrtko Ursulin 2021-05-27 14:37 ` Matthew Brost 2021-05-27 14:37 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 56/97] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 57/97] drm/i915/guc: Add several request trace points Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 58/97] drm/i915: Add intel_context tracing Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 59/97] drm/i915/guc: GuC virtual engines Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 60/97] drm/i915: Track 'serial' counts for " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-25 10:16 ` Tvrtko Ursulin 2021-05-25 10:16 ` Tvrtko Ursulin 2021-05-25 17:52 ` Matthew Brost 2021-05-25 17:52 ` Matthew Brost 2021-05-26 8:40 ` Tvrtko Ursulin 2021-05-26 8:40 ` Tvrtko Ursulin 2021-05-26 18:45 ` John Harrison 2021-05-26 18:45 ` John Harrison 2021-05-27 8:53 ` Tvrtko Ursulin 2021-05-27 8:53 ` Tvrtko Ursulin 2021-05-27 17:01 ` John Harrison 2021-05-27 17:01 ` John Harrison 2021-06-01 9:31 ` Tvrtko Ursulin 2021-06-01 9:31 ` Tvrtko Ursulin 2021-06-02 1:20 ` John Harrison 2021-06-02 1:20 ` John Harrison 2021-06-02 12:04 ` Tvrtko Ursulin 2021-06-02 12:04 ` Tvrtko Ursulin 2021-06-02 12:09 ` Tvrtko Ursulin 2021-06-02 12:09 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 61/97] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 12:18 ` Tvrtko Ursulin 2021-06-02 12:18 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 62/97] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 63/97] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 13:31 ` Tvrtko Ursulin 2021-06-02 13:31 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 64/97] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 14:33 ` Tvrtko Ursulin 2021-06-02 14:33 ` Tvrtko Ursulin 2021-06-04 3:17 ` Matthew Brost 2021-06-04 3:17 ` Matthew Brost 2021-06-04 8:16 ` Daniel Vetter 2021-06-04 8:16 ` Daniel Vetter 2021-06-04 18:02 ` Matthew Brost 2021-06-04 18:02 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 65/97] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 14:36 ` Tvrtko Ursulin 2021-06-02 14:36 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 66/97] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 8:16 ` [drm/i915/guc] 07336fb545: WARNING:at_drivers/gpu/drm/i915/gt/uc/intel_uc.c:#__uc_sanitize[i915] kernel test robot 2021-05-11 8:16 ` kernel test robot 2021-05-11 8:16 ` [Intel-gfx] " kernel test robot 2021-05-11 8:16 ` kernel test robot 2021-05-06 19:14 ` [RFC PATCH 67/97] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 68/97] drm/i915/guc: Handle context reset notification Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 16:25 ` Daniel Vetter 2021-05-11 16:25 ` Daniel Vetter 2021-05-06 19:14 ` [RFC PATCH 69/97] drm/i915/guc: Handle engine reset failure notification Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 70/97] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 71/97] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 72/97] drm/i915/guc: Don't complain about reset races Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 73/97] drm/i915/guc: Enable GuC engine reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 74/97] drm/i915/guc: Capture error state on context reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 16:28 ` Daniel Vetter 2021-05-11 16:28 ` Daniel Vetter 2021-05-11 17:12 ` Matthew Brost 2021-05-11 17:12 ` Matthew Brost 2021-05-11 17:45 ` Daniel Vetter 2021-05-11 17:45 ` Daniel Vetter 2021-05-06 19:14 ` [RFC PATCH 75/97] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 76/97] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 77/97] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 78/97] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 79/97] drm/i915/guc: Don't call ring_is_idle in GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 80/97] drm/i915/guc: Implement banned contexts for " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 81/97] drm/i915/guc: Allow flexible number of context ids Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 82/97] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 83/97] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-07 6:06 ` kernel test robot 2021-05-06 19:14 ` Matthew Brost [this message] 2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 85/97] drm/i915/guc: Introduce guc_submit_engine object Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 86/97] drm/i915/guc: Add golden context to GuC ADS Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 87/97] drm/i915/guc: Implement GuC priority management Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 88/97] drm/i915/guc: Support request cancellation Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 89/97] drm/i915/guc: Check return of __xa_store when registering a context Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 90/97] drm/i915/guc: Non-static lrc descriptor registration buffer Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 91/97] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 92/97] drm/i915: Add GT PM delayed worker Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 93/97] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 94/97] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 95/97] drm/i915/guc: Selftest for GuC flow control Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 96/97] drm/i915/guc: Update GuC documentation Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 97/97] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-09 17:12 ` [RFC PATCH 00/97] Basic GuC submission support in the i915 Martin Peres 2021-05-09 17:12 ` [Intel-gfx] " Martin Peres 2021-05-09 23:11 ` Jason Ekstrand 2021-05-09 23:11 ` [Intel-gfx] " Jason Ekstrand 2021-05-10 13:55 ` Martin Peres 2021-05-10 13:55 ` [Intel-gfx] " Martin Peres 2021-05-10 16:25 ` Jason Ekstrand 2021-05-10 16:25 ` [Intel-gfx] " Jason Ekstrand 2021-05-11 8:01 ` Martin Peres 2021-05-11 8:01 ` [Intel-gfx] " Martin Peres 2021-05-10 16:33 ` Daniel Vetter 2021-05-10 16:33 ` [Intel-gfx] " Daniel Vetter 2021-05-10 18:30 ` Francisco Jerez 2021-05-10 18:30 ` Francisco Jerez 2021-05-11 8:06 ` Martin Peres 2021-05-11 8:06 ` [Intel-gfx] " Martin Peres 2021-05-11 15:26 ` Bloomfield, Jon 2021-05-11 15:26 ` [Intel-gfx] " Bloomfield, Jon 2021-05-11 16:39 ` Matthew Brost 2021-05-11 16:39 ` [Intel-gfx] " Matthew Brost 2021-05-12 6:26 ` Martin Peres 2021-05-12 6:26 ` [Intel-gfx] " Martin Peres 2021-05-14 16:31 ` Jason Ekstrand 2021-05-14 16:31 ` [Intel-gfx] " Jason Ekstrand 2021-05-25 15:37 ` Alex Deucher 2021-05-25 15:37 ` [Intel-gfx] " Alex Deucher 2021-05-11 2:58 ` Dixit, Ashutosh 2021-05-11 2:58 ` [Intel-gfx] " Dixit, Ashutosh 2021-05-11 7:47 ` Martin Peres 2021-05-11 7:47 ` [Intel-gfx] " Martin Peres 2021-05-14 11:11 ` Tvrtko Ursulin 2021-05-14 11:11 ` Tvrtko Ursulin 2021-05-14 16:36 ` Jason Ekstrand 2021-05-14 16:36 ` Jason Ekstrand 2021-05-14 16:46 ` Matthew Brost 2021-05-14 16:46 ` Matthew Brost 2021-05-14 16:41 ` Matthew Brost 2021-05-14 16:41 ` Matthew Brost 2021-05-25 10:32 ` Tvrtko Ursulin 2021-05-25 10:32 ` Tvrtko Ursulin 2021-05-25 16:45 ` Matthew Brost 2021-05-25 16:45 ` Matthew Brost 2021-06-02 15:27 ` Tvrtko Ursulin 2021-06-02 15:27 ` Tvrtko Ursulin 2021-06-02 18:57 ` Daniel Vetter 2021-06-02 18:57 ` Daniel Vetter 2021-06-03 3:41 ` Matthew Brost 2021-06-03 3:41 ` Matthew Brost 2021-06-03 4:47 ` Daniel Vetter 2021-06-03 4:47 ` Daniel Vetter 2021-06-03 9:49 ` Tvrtko Ursulin 2021-06-03 9:49 ` Tvrtko Ursulin 2021-06-03 10:52 ` Tvrtko Ursulin 2021-06-03 10:52 ` Tvrtko Ursulin 2021-06-03 4:10 ` Matthew Brost 2021-06-03 4:10 ` Matthew Brost 2021-06-03 8:51 ` Tvrtko Ursulin 2021-06-03 8:51 ` Tvrtko Ursulin 2021-06-03 16:34 ` Matthew Brost 2021-06-03 16:34 ` Matthew Brost
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