From: Bjorn Andersson <bjorn.andersson@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] dpu: hack up the irq table for 8180 intf_5 Date: Mon, 10 May 2021 23:18:52 -0500 [thread overview] Message-ID: <20210511041852.592295-5-bjorn.andersson@linaro.org> (raw) In-Reply-To: <20210511041852.592295-1-bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- This is a hack and as discussed on IRC this should be replaced by some sane mechanism for dealing with the old and new IRQ layout. Including it in the series for completeness. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 48c96b812126..fa576c617f86 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -72,11 +72,13 @@ #define DPU_INTR_INTF_1_UNDERRUN BIT(26) #define DPU_INTR_INTF_2_UNDERRUN BIT(28) #define DPU_INTR_INTF_3_UNDERRUN BIT(30) +#define DPU_INTR_INTF_4_UNDERRUN BIT(20) #define DPU_INTR_INTF_5_UNDERRUN BIT(22) #define DPU_INTR_INTF_0_VSYNC BIT(25) #define DPU_INTR_INTF_1_VSYNC BIT(27) #define DPU_INTR_INTF_2_VSYNC BIT(29) #define DPU_INTR_INTF_3_VSYNC BIT(31) +#define DPU_INTR_INTF_4_VSYNC BIT(21) #define DPU_INTR_INTF_5_VSYNC BIT(23) /** @@ -310,14 +312,10 @@ static const struct dpu_irq_type dpu_irq_map[] = { { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3, DPU_INTR_PING_PONG_3_WR_PTR, 0}, /* irq_idx: 20-23 */ - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0, - DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1, - DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2, - DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3, - DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0}, + { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_4, DPU_INTR_INTF_4_UNDERRUN, 0}, + { DPU_IRQ_TYPE_INTF_VSYNC, INTF_4, DPU_INTR_INTF_4_VSYNC, 0}, + { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0}, + { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0}, /* irq_idx: 24-27 */ { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0}, { DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0}, -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Andersson <bjorn.andersson@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH 4/4] dpu: hack up the irq table for 8180 intf_5 Date: Mon, 10 May 2021 23:18:52 -0500 [thread overview] Message-ID: <20210511041852.592295-5-bjorn.andersson@linaro.org> (raw) In-Reply-To: <20210511041852.592295-1-bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- This is a hack and as discussed on IRC this should be replaced by some sane mechanism for dealing with the old and new IRQ layout. Including it in the series for completeness. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 48c96b812126..fa576c617f86 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -72,11 +72,13 @@ #define DPU_INTR_INTF_1_UNDERRUN BIT(26) #define DPU_INTR_INTF_2_UNDERRUN BIT(28) #define DPU_INTR_INTF_3_UNDERRUN BIT(30) +#define DPU_INTR_INTF_4_UNDERRUN BIT(20) #define DPU_INTR_INTF_5_UNDERRUN BIT(22) #define DPU_INTR_INTF_0_VSYNC BIT(25) #define DPU_INTR_INTF_1_VSYNC BIT(27) #define DPU_INTR_INTF_2_VSYNC BIT(29) #define DPU_INTR_INTF_3_VSYNC BIT(31) +#define DPU_INTR_INTF_4_VSYNC BIT(21) #define DPU_INTR_INTF_5_VSYNC BIT(23) /** @@ -310,14 +312,10 @@ static const struct dpu_irq_type dpu_irq_map[] = { { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3, DPU_INTR_PING_PONG_3_WR_PTR, 0}, /* irq_idx: 20-23 */ - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0, - DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1, - DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2, - DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3, - DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0}, + { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_4, DPU_INTR_INTF_4_UNDERRUN, 0}, + { DPU_IRQ_TYPE_INTF_VSYNC, INTF_4, DPU_INTR_INTF_4_VSYNC, 0}, + { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0}, + { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0}, /* irq_idx: 24-27 */ { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0}, { DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0}, -- 2.29.2
next prev parent reply other threads:[~2021-05-11 4:19 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-11 4:18 [PATCH 0/4] drm/msm/dpu: Qualcomm SC8180x MDSS/DPU support Bjorn Andersson 2021-05-11 4:18 ` Bjorn Andersson 2021-05-11 4:18 ` [PATCH 1/4] drm/msm/dpu: Introduce knowledge of widebus feature Bjorn Andersson 2021-05-11 4:18 ` Bjorn Andersson 2021-05-12 23:14 ` Dmitry Baryshkov 2021-05-12 23:14 ` Dmitry Baryshkov 2021-05-11 4:18 ` [PATCH 2/4] drm/msm/dpu: Clear boot loader configured data paths Bjorn Andersson 2021-05-11 4:18 ` Bjorn Andersson 2021-05-12 23:06 ` Dmitry Baryshkov 2021-05-12 23:06 ` Dmitry Baryshkov 2021-05-11 4:18 ` [PATCH 3/4] drm/msm/dpu: Add SC8180x to hw catalog Bjorn Andersson 2021-05-11 4:18 ` Bjorn Andersson 2021-05-12 22:58 ` Dmitry Baryshkov 2021-05-12 22:58 ` Dmitry Baryshkov 2021-05-16 4:25 ` Bjorn Andersson 2021-05-16 4:25 ` Bjorn Andersson 2021-05-17 21:43 ` Rob Herring 2021-05-17 21:43 ` Rob Herring 2021-05-11 4:18 ` Bjorn Andersson [this message] 2021-05-11 4:18 ` [PATCH 4/4] dpu: hack up the irq table for 8180 intf_5 Bjorn Andersson
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