From: Fuad Tabba <tabba@google.com>
To: linux-arm-kernel@lists.infradead.org
Cc: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com,
maz@kernel.org, ardb@kernel.org, james.morse@arm.com,
alexandru.elisei@arm.com, suzuki.poulose@arm.com,
tabba@google.com
Subject: [PATCH v1 01/13] arm64: Do not enable uaccess for flush_icache_range
Date: Tue, 11 May 2021 15:42:40 +0100 [thread overview]
Message-ID: <20210511144252.3779113-2-tabba@google.com> (raw)
In-Reply-To: <20210511144252.3779113-1-tabba@google.com>
__flush_icache_range works on the kernel linear map, and doesn't
need uaccess. The existing code is a side-effect of its current
implementation with __flush_cache_user_range fallthrough.
Instead of fallthrough to share the code, use a common macro for
the two where the caller can specify whether user-space access is
needed.
No functional change intended.
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/
Signed-off-by: Fuad Tabba <tabba@google.com>
---
arch/arm64/include/asm/assembler.h | 13 ++++--
arch/arm64/mm/cache.S | 64 +++++++++++++++++++++---------
2 files changed, 54 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 8418c1bd8f04..6ff7a3a3b238 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -426,16 +426,21 @@ alternative_endif
* Macro to perform an instruction cache maintenance for the interval
* [start, end)
*
- * start, end: virtual addresses describing the region
- * label: A label to branch to on user fault.
- * Corrupts: tmp1, tmp2
+ * start, end: virtual addresses describing the region
+ * needs_uaccess: might access user space memory
+ * label: label to branch to on user fault (if needs_uaccess)
+ * Corrupts: tmp1, tmp2
*/
- .macro invalidate_icache_by_line start, end, tmp1, tmp2, label
+ .macro invalidate_icache_by_line start, end, tmp1, tmp2, needs_uaccess, label
icache_line_size \tmp1, \tmp2
sub \tmp2, \tmp1, #1
bic \tmp2, \start, \tmp2
9997:
+ .if \needs_uaccess
USER(\label, ic ivau, \tmp2) // invalidate I line PoU
+ .else
+ ic ivau, \tmp2
+ .endif
add \tmp2, \tmp2, \tmp1
cmp \tmp2, \end
b.lo 9997b
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 2d881f34dd9d..092f73acdf9a 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -15,30 +15,20 @@
#include <asm/asm-uaccess.h>
/*
- * flush_icache_range(start,end)
+ * __flush_cache_range(start,end) [needs_uaccess]
*
* Ensure that the I and D caches are coherent within specified region.
* This is typically used when code has been written to a memory region,
* and will be executed.
*
- * - start - virtual start address of region
- * - end - virtual end address of region
+ * - start - virtual start address of region
+ * - end - virtual end address of region
+ * - needs_uaccess - (macro parameter) might access user space memory
*/
-SYM_FUNC_START(__flush_icache_range)
- /* FALLTHROUGH */
-
-/*
- * __flush_cache_user_range(start,end)
- *
- * Ensure that the I and D caches are coherent within specified region.
- * This is typically used when code has been written to a memory region,
- * and will be executed.
- *
- * - start - virtual start address of region
- * - end - virtual end address of region
- */
-SYM_FUNC_START(__flush_cache_user_range)
+.macro __flush_cache_range, needs_uaccess
+ .if \needs_uaccess
uaccess_ttbr0_enable x2, x3, x4
+ .endif
alternative_if ARM64_HAS_CACHE_IDC
dsb ishst
b 7f
@@ -47,7 +37,11 @@ alternative_else_nop_endif
sub x3, x2, #1
bic x4, x0, x3
1:
+ .if \needs_uaccess
user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
+ .else
+alternative_insn "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
+ .endif
add x4, x4, x2
cmp x4, x1
b.lo 1b
@@ -58,15 +52,47 @@ alternative_if ARM64_HAS_CACHE_DIC
isb
b 8f
alternative_else_nop_endif
- invalidate_icache_by_line x0, x1, x2, x3, 9f
+ invalidate_icache_by_line x0, x1, x2, x3, \needs_uaccess, 9f
8: mov x0, #0
1:
+ .if \needs_uaccess
uaccess_ttbr0_disable x1, x2
+ .endif
ret
+
+ .if \needs_uaccess
9:
mov x0, #-EFAULT
b 1b
+ .endif
+.endm
+
+/*
+ * flush_icache_range(start,end)
+ *
+ * Ensure that the I and D caches are coherent within specified region.
+ * This is typically used when code has been written to a memory region,
+ * and will be executed.
+ *
+ * - start - virtual start address of region
+ * - end - virtual end address of region
+ */
+SYM_FUNC_START(__flush_icache_range)
+ __flush_cache_range needs_uaccess=0
SYM_FUNC_END(__flush_icache_range)
+
+/*
+ * __flush_cache_user_range(start,end)
+ *
+ * Ensure that the I and D caches are coherent within specified region.
+ * This is typically used when code has been written to a memory region,
+ * and will be executed.
+ *
+ * - start - virtual start address of region
+ * - end - virtual end address of region
+ */
+SYM_FUNC_START(__flush_cache_user_range)
+ __flush_cache_range needs_uaccess=1
SYM_FUNC_END(__flush_cache_user_range)
/*
@@ -86,7 +112,7 @@ alternative_else_nop_endif
uaccess_ttbr0_enable x2, x3, x4
- invalidate_icache_by_line x0, x1, x2, x3, 2f
+ invalidate_icache_by_line x0, x1, x2, x3, 1, 2f
mov x0, xzr
1:
uaccess_ttbr0_disable x1, x2
--
2.31.1.607.g51e8a6a459-goog
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next prev parent reply other threads:[~2021-05-11 14:44 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 14:42 [PATCH v1 00/13] Tidy up cache.S Fuad Tabba
2021-05-11 14:42 ` Fuad Tabba [this message]
2021-05-11 15:22 ` [PATCH v1 01/13] arm64: Do not enable uaccess for flush_icache_range Mark Rutland
2021-05-12 8:52 ` Fuad Tabba
2021-05-12 9:59 ` Mark Rutland
2021-05-12 10:29 ` Fuad Tabba
2021-05-12 10:53 ` Mark Rutland
2021-05-11 16:53 ` Robin Murphy
2021-05-12 8:57 ` Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 02/13] arm64: Do not enable uaccess for invalidate_icache_range Fuad Tabba
2021-05-11 15:34 ` Mark Rutland
2021-05-12 9:35 ` Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 03/13] arm64: Downgrade flush_icache_range to invalidate Fuad Tabba
2021-05-11 14:53 ` Ard Biesheuvel
2021-05-12 9:45 ` Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 04/13] arm64: Move documentation of dcache_by_line_op Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 05/13] arm64: __inval_dcache_area to take end parameter instead of size Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 06/13] arm64: dcache_by_line_op " Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 07/13] arm64: __flush_dcache_area " Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 08/13] arm64: __clean_dcache_area_poc " Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 09/13] arm64: __clean_dcache_area_pop " Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 10/13] arm64: __clean_dcache_area_pou " Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 11/13] arm64: sync_icache_aliases " Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 12/13] arm64: Fix cache maintenance function comments Fuad Tabba
2021-05-11 14:42 ` [PATCH v1 13/13] arm64: Rename arm64-internal cache maintenance functions Fuad Tabba
2021-05-11 15:09 ` Ard Biesheuvel
2021-05-11 15:49 ` Mark Rutland
2021-05-12 9:51 ` Marc Zyngier
2021-05-12 10:00 ` Mark Rutland
2021-05-12 10:00 ` Fuad Tabba
2021-05-12 10:04 ` Mark Rutland
2021-05-12 9:56 ` Fuad Tabba
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