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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: Replace intel_dp_set_infoframes() enable calls by dig_port->set_infoframes()
Date: Thu, 13 May 2021 22:28:42 -0700	[thread overview]
Message-ID: <20210514052843.9456-3-jose.souza@intel.com> (raw)
In-Reply-To: <20210514052843.9456-1-jose.souza@intel.com>

intel_dp_set_infoframes() and set_infoframes() hook had some code
overlapping that makes sense us try to drop it.

set_infoframes() is called during the pre_enable phase while
intel_dp_set_infoframes() was being called in the enable phase but
it was only enabling DP_SDP_VSC and HDMI_PACKET_TYPE_GAMUT_METADATA
infoframes, that were added back to hsw_set_infoframes() and
lspcon_set_infoframes().

Did not found any information about why this difference of phase but
if it is not supported our CI will probably catch it.

As hsw_set_infoframes() will now be called during the fastset updates
the assert_hdmi_transcoder_func_disabled() check needed to be dropped.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c    | 11 ++-----
 drivers/gpu/drm/i915/display/intel_dp.c     | 36 ++-------------------
 drivers/gpu/drm/i915/display/intel_dp.h     |  6 ++--
 drivers/gpu/drm/i915/display/intel_hdmi.c   | 19 ++++-------
 drivers/gpu/drm/i915/display/intel_lspcon.c |  2 ++
 5 files changed, 17 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ba2f98881638..04cf7815da2f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2762,9 +2762,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
 					conn_state);
 
 		/* FIXME precompute everything properly */
-		if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
-			dig_port->set_infoframes(encoder, true, crtc_state,
-						 conn_state);
+		dig_port->set_infoframes(encoder, true, crtc_state, conn_state);
 	}
 }
 
@@ -3033,7 +3031,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	enum port port = encoder->port;
 
 	if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
@@ -3042,9 +3039,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state, conn_state);
 
-	if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
-		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
-
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
@@ -3245,12 +3239,13 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
 				     const struct intel_crtc_state *crtc_state,
 				     const struct drm_connector_state *conn_state)
 {
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
 	intel_psr_update(intel_dp, crtc_state, conn_state);
-	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+	dig_port->set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_update(intel_dp, crtc_state);
 
 	intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 861409bc210d..270d9d7ac614 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2757,9 +2757,9 @@ intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_in
 	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
 }
 
-static void intel_write_dp_sdp(struct intel_encoder *encoder,
-			       const struct intel_crtc_state *crtc_state,
-			       unsigned int type)
+void intel_write_dp_sdp(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
+			unsigned int type)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2808,36 +2808,6 @@ void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
 					&sdp, len);
 }
 
-void intel_dp_set_infoframes(struct intel_encoder *encoder,
-			     bool enable,
-			     const struct intel_crtc_state *crtc_state,
-			     const struct drm_connector_state *conn_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
-	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
-			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
-			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
-	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
-
-	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
-	/* When PSR is enabled, this routine doesn't disable VSC DIP */
-	if (!crtc_state->has_psr)
-		val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
-
-	intel_de_write(dev_priv, reg, val);
-	intel_de_posting_read(dev_priv, reg);
-
-	if (!enable)
-		return;
-
-	/* When PSR is enabled, VSC SDP is handled by PSR routine */
-	if (!crtc_state->has_psr)
-		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
-
-	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
-}
-
 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
 				   const void *buffer, size_t size)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 680631b5b437..be5ad619d573 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -99,9 +99,9 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state,
 			    struct drm_dp_vsc_sdp *vsc);
-void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
-			     const struct intel_crtc_state *crtc_state,
-			     const struct drm_connector_state *conn_state);
+void intel_write_dp_sdp(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
+			unsigned int type);
 void intel_read_dp_sdp(struct intel_encoder *encoder,
 		       struct intel_crtc_state *crtc_state,
 		       unsigned int type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 4b970587067d..fd656370053b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -71,16 +71,6 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
 		 "HDMI port enabled, expecting disabled\n");
 }
 
-static void
-assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
-				     enum transcoder cpu_transcoder)
-{
-	drm_WARN(&dev_priv->drm,
-		 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
-		 TRANS_DDI_FUNC_ENABLE,
-		 "HDMI transcoder function enabled, expecting disabled\n");
-}
-
 static u32 g4x_infoframe_index(unsigned int type)
 {
 	switch (type) {
@@ -1209,9 +1199,6 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 	u32 val = intel_de_read(dev_priv, reg);
 
-	assert_hdmi_transcoder_func_disabled(dev_priv,
-					     crtc_state->cpu_transcoder);
-
 	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
@@ -1241,6 +1228,12 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
 	intel_write_infoframe(encoder, crtc_state,
 			      HDMI_INFOFRAME_TYPE_DRM,
 			      &crtc_state->infoframes.drm);
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (!crtc_state->has_psr)
+		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+
+	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 05d2d750fa53..e4105156822b 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -565,6 +565,8 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
 
 	dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI,
 				  buf, ret);
+
+	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
 static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
-- 
2.31.1

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  parent reply	other threads:[~2021-05-14  5:25 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14  5:28 [Intel-gfx] [PATCH 1/4] drm/i915/display: Nuke has_infoframe José Roberto de Souza
2021-05-14  5:28 ` [Intel-gfx] [PATCH 2/4] drm/i915/display: Replace intel_dp_set_infoframes() disable calls by dig_port->set_infoframes() José Roberto de Souza
2021-05-14  5:28 ` José Roberto de Souza [this message]
2021-05-14  5:28 ` [Intel-gfx] [PATCH 4/4] drm/i915/display: Fix fastsets involving PSR José Roberto de Souza
2021-05-14  5:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/display: Nuke has_infoframe Patchwork
2021-05-14  6:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-14  8:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-14 23:21 ` [Intel-gfx] [PATCH 1/4] " Souza, Jose

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