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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 16/19] drm/i915/adl_p: Add IPs stepping mapping
Date: Fri, 14 May 2021 08:37:08 -0700	[thread overview]
Message-ID: <20210514153711.2359617-17-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210514153711.2359617-1-matthew.d.roper@intel.com>

From: José Roberto de Souza <jose.souza@intel.com>

This will allow us to better implement workarounds.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  8 ++++++++
 drivers/gpu/drm/i915/intel_step.c | 12 +++++++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 61308ce19059..39b5e019c1a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1551,6 +1551,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_ALDERLAKE_S(__i915) && \
 	 IS_GT_STEP(__i915, since, until))
 
+#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
+	(IS_ALDERLAKE_P(__i915) && \
+	 IS_DISPLAY_STEP(__i915, since, until))
+
+#define IS_ADLP_GT_STEP(__i915, since, until) \
+	(IS_ALDERLAKE_P(__i915) && \
+	 IS_GT_STEP(__i915, since, until))
+
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 4d71547a5b83..ba9479a67521 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -47,6 +47,13 @@ static const struct intel_step_info adls_revid_step_tbl[] = {
 	[0xC] = { .gt_step = STEP_D0, .display_step = STEP_C0 },
 };
 
+static const struct intel_step_info adlp_revid_step_tbl[] = {
+	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+	[0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+	[0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
+	[0xC] = { .gt_step = STEP_C0, .display_step = STEP_D0 },
+};
+
 void intel_step_init(struct drm_i915_private *i915)
 {
 	const struct intel_step_info *revids = NULL;
@@ -54,7 +61,10 @@ void intel_step_init(struct drm_i915_private *i915)
 	int revid = INTEL_REVID(i915);
 	struct intel_step_info step = {};
 
-	if (IS_ALDERLAKE_S(i915)) {
+	if (IS_ALDERLAKE_P(i915)) {
+		revids = adlp_revid_step_tbl;
+		size = ARRAY_SIZE(adlp_revid_step_tbl);
+	} else if (IS_ALDERLAKE_S(i915)) {
 		revids = adls_revid_step_tbl;
 		size = ARRAY_SIZE(adls_revid_step_tbl);
 	} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
-- 
2.25.4

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  parent reply	other threads:[~2021-05-14 15:37 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 01/19] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 02/19] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 03/19] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 04/19] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 05/19] drm/i915: Get slice height before computing rc params Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 06/19] drm/i915/xelpd: Provide port/phy mapping for vbt Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 07/19] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 08/19] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 09/19] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 10/19] drm/i915/adl_p: Enable modular fia Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 11/19] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 12/19] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 13/19] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 14/19] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-06-03  9:39   ` Jani Nikula
2021-06-03 12:33     ` Jani Nikula
2021-06-03 13:49       ` Manna, Animesh
2021-06-03 18:27         ` Navare, Manasi
2021-06-04  9:11           ` Jani Nikula
2021-06-03 13:37     ` Manna, Animesh
2021-06-03 15:41       ` Jani Nikula
2021-06-04  8:54         ` Manna, Animesh
2021-05-14 15:37 ` Matt Roper [this message]
2021-05-14 15:37 ` [Intel-gfx] [CI 17/19] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 18/19] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 19/19] drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057) Matt Roper
2021-05-14 16:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Another batch of reviewed XeLPD / ADL-P patches Patchwork
2021-05-14 16:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-14 17:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-15  2:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-15  3:00   ` Matt Roper

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