From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: Michal.Wajdeczko@intel.com Subject: [PATCH 14/17] drm/i915/guc: Ensure H2G buffer updates visible before tail update Date: Tue, 25 May 2021 14:15:38 -0700 [thread overview] Message-ID: <20210525211541.87696-15-matthew.brost@intel.com> (raw) In-Reply-To: <20210525211541.87696-1-matthew.brost@intel.com> Ensure H2G buffer updates are visible before descriptor tail updates by inserting a barrier between the H2G buffer update and the tail. The barrier is simple wmb() for SMEM and is register write for LMEM. This is needed if more than 1 H2G can be inflight at once. Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index e44f06fbf87a..732a8ffa52dc 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -328,6 +328,18 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct) return ++ct->requests.last_fence; } +static void write_barrier(struct intel_guc_ct *ct) { + struct intel_guc *guc = ct_to_guc(ct); + struct intel_gt *gt = guc_to_gt(guc); + + if (i915_gem_object_is_lmem(guc->ct.vma->obj)) { + GEM_BUG_ON(guc->send_regs.fw_domains); + intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0); + } else { + wmb(); + } +} + /** * DOC: CTB Host to GuC request * @@ -411,6 +423,12 @@ static int ct_write(struct intel_guc_ct *ct, } GEM_BUG_ON(tail > size); + /* + * make sure H2G buffer update and LRC tail update (if this triggering a + * submission) are visible before updating the descriptor tail + */ + write_barrier(ct); + /* now update desc tail (back in bytes) */ desc->tail = tail * 4; return 0; -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Subject: [Intel-gfx] [PATCH 14/17] drm/i915/guc: Ensure H2G buffer updates visible before tail update Date: Tue, 25 May 2021 14:15:38 -0700 [thread overview] Message-ID: <20210525211541.87696-15-matthew.brost@intel.com> (raw) In-Reply-To: <20210525211541.87696-1-matthew.brost@intel.com> Ensure H2G buffer updates are visible before descriptor tail updates by inserting a barrier between the H2G buffer update and the tail. The barrier is simple wmb() for SMEM and is register write for LMEM. This is needed if more than 1 H2G can be inflight at once. Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index e44f06fbf87a..732a8ffa52dc 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -328,6 +328,18 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct) return ++ct->requests.last_fence; } +static void write_barrier(struct intel_guc_ct *ct) { + struct intel_guc *guc = ct_to_guc(ct); + struct intel_gt *gt = guc_to_gt(guc); + + if (i915_gem_object_is_lmem(guc->ct.vma->obj)) { + GEM_BUG_ON(guc->send_regs.fw_domains); + intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0); + } else { + wmb(); + } +} + /** * DOC: CTB Host to GuC request * @@ -411,6 +423,12 @@ static int ct_write(struct intel_guc_ct *ct, } GEM_BUG_ON(tail > size); + /* + * make sure H2G buffer update and LRC tail update (if this triggering a + * submission) are visible before updating the descriptor tail + */ + write_barrier(ct); + /* now update desc tail (back in bytes) */ desc->tail = tail * 4; return 0; -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-05-25 20:58 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-25 21:15 [PATCH 00/17] Non-interface changing GuC CTBs updates Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2021-05-25 21:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-05-25 21:15 ` [PATCH 01/17] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 02/17] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 03/17] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 04/17] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 05/17] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 06/17] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 07/17] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 08/17] drm/i915/guc: Only rely on own CTB size Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 09/17] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 10/17] drm/i915/guc: Replace CTB array with explicit members Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 11/17] drm/i915/guc: Update sizes of CTB buffers Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 12/17] drm/i915/guc: Relax CTB response timeout Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 13/17] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` Matthew Brost [this message] 2021-05-25 21:15 ` [Intel-gfx] [PATCH 14/17] drm/i915/guc: Ensure H2G buffer updates visible before tail update Matthew Brost 2021-05-25 21:15 ` [PATCH 15/17] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 16/17] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:15 ` [PATCH 17/17] drm/i915/guc: Always copy CT message to new allocation Matthew Brost 2021-05-25 21:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 21:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Non-interface changing GuC CTBs updates Patchwork 2021-05-26 3:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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