From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: Michal.Wajdeczko@intel.com Subject: [PATCH 03/18] drm/i915/guc: enable only the user interrupt when using GuC submission Date: Tue, 25 May 2021 23:42:22 -0700 [thread overview] Message-ID: <20210526064237.77853-4-matthew.brost@intel.com> (raw) In-Reply-To: <20210526064237.77853-1-matthew.brost@intel.com> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> In GuC submission mode the CS is owned by the GuC FW, so all CS status interrupts are handled by it. We only need the user interrupt as that signals request completion. Since we're now starting the engines directly in GuC submission mode when selected, we can stop switching back and forth between the execlists and the GuC programming and select directly the correct interrupt mask. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Cc: John Harrison <john.c.harrison@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 18 ++++++----- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 31 ------------------- 2 files changed, 11 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index d29126c458ba..f88c10366e58 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -194,14 +194,18 @@ void gen11_gt_irq_reset(struct intel_gt *gt) void gen11_gt_irq_postinstall(struct intel_gt *gt) { - const u32 irqs = - GT_CS_MASTER_ERROR_INTERRUPT | - GT_RENDER_USER_INTERRUPT | - GT_CONTEXT_SWITCH_INTERRUPT | - GT_WAIT_SEMAPHORE_INTERRUPT; struct intel_uncore *uncore = gt->uncore; - const u32 dmask = irqs << 16 | irqs; - const u32 smask = irqs << 16; + u32 irqs = GT_RENDER_USER_INTERRUPT; + u32 dmask; + u32 smask; + + if (!intel_uc_wants_guc_submission(>->uc)) + irqs |= GT_CS_MASTER_ERROR_INTERRUPT | + GT_CONTEXT_SWITCH_INTERRUPT | + GT_WAIT_SEMAPHORE_INTERRUPT; + + dmask = irqs << 16 | irqs; + smask = irqs << 16; BUILD_BUG_ON(irqs & 0xffff0000); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 335719f17490..38cda5d599a6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -432,32 +432,6 @@ void intel_guc_submission_fini(struct intel_guc *guc) } } -static void guc_interrupts_capture(struct intel_gt *gt) -{ - struct intel_uncore *uncore = gt->uncore; - u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; - u32 dmask = irqs << 16 | irqs; - - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11); - - /* Don't handle the ctx switch interrupt in GuC submission mode */ - intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0); - intel_uncore_rmw(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask, 0); -} - -static void guc_interrupts_release(struct intel_gt *gt) -{ - struct intel_uncore *uncore = gt->uncore; - u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; - u32 dmask = irqs << 16 | irqs; - - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11); - - /* Handle ctx switch interrupts again */ - intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask); - intel_uncore_rmw(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0, dmask); -} - static int guc_context_alloc(struct intel_context *ce) { return lrc_alloc(ce, ce->engine); @@ -722,9 +696,6 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine) void intel_guc_submission_enable(struct intel_guc *guc) { guc_stage_desc_init(guc); - - /* Take over from manual control of ELSP (execlists) */ - guc_interrupts_capture(guc_to_gt(guc)); } void intel_guc_submission_disable(struct intel_guc *guc) @@ -735,8 +706,6 @@ void intel_guc_submission_disable(struct intel_guc *guc) /* Note: By the time we're here, GuC may have already been reset */ - guc_interrupts_release(gt); - guc_stage_desc_fini(guc); } -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Subject: [Intel-gfx] [PATCH 03/18] drm/i915/guc: enable only the user interrupt when using GuC submission Date: Tue, 25 May 2021 23:42:22 -0700 [thread overview] Message-ID: <20210526064237.77853-4-matthew.brost@intel.com> (raw) In-Reply-To: <20210526064237.77853-1-matthew.brost@intel.com> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> In GuC submission mode the CS is owned by the GuC FW, so all CS status interrupts are handled by it. We only need the user interrupt as that signals request completion. Since we're now starting the engines directly in GuC submission mode when selected, we can stop switching back and forth between the execlists and the GuC programming and select directly the correct interrupt mask. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Cc: John Harrison <john.c.harrison@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 18 ++++++----- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 31 ------------------- 2 files changed, 11 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index d29126c458ba..f88c10366e58 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -194,14 +194,18 @@ void gen11_gt_irq_reset(struct intel_gt *gt) void gen11_gt_irq_postinstall(struct intel_gt *gt) { - const u32 irqs = - GT_CS_MASTER_ERROR_INTERRUPT | - GT_RENDER_USER_INTERRUPT | - GT_CONTEXT_SWITCH_INTERRUPT | - GT_WAIT_SEMAPHORE_INTERRUPT; struct intel_uncore *uncore = gt->uncore; - const u32 dmask = irqs << 16 | irqs; - const u32 smask = irqs << 16; + u32 irqs = GT_RENDER_USER_INTERRUPT; + u32 dmask; + u32 smask; + + if (!intel_uc_wants_guc_submission(>->uc)) + irqs |= GT_CS_MASTER_ERROR_INTERRUPT | + GT_CONTEXT_SWITCH_INTERRUPT | + GT_WAIT_SEMAPHORE_INTERRUPT; + + dmask = irqs << 16 | irqs; + smask = irqs << 16; BUILD_BUG_ON(irqs & 0xffff0000); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 335719f17490..38cda5d599a6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -432,32 +432,6 @@ void intel_guc_submission_fini(struct intel_guc *guc) } } -static void guc_interrupts_capture(struct intel_gt *gt) -{ - struct intel_uncore *uncore = gt->uncore; - u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; - u32 dmask = irqs << 16 | irqs; - - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11); - - /* Don't handle the ctx switch interrupt in GuC submission mode */ - intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0); - intel_uncore_rmw(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask, 0); -} - -static void guc_interrupts_release(struct intel_gt *gt) -{ - struct intel_uncore *uncore = gt->uncore; - u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; - u32 dmask = irqs << 16 | irqs; - - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11); - - /* Handle ctx switch interrupts again */ - intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask); - intel_uncore_rmw(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0, dmask); -} - static int guc_context_alloc(struct intel_context *ce) { return lrc_alloc(ce, ce->engine); @@ -722,9 +696,6 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine) void intel_guc_submission_enable(struct intel_guc *guc) { guc_stage_desc_init(guc); - - /* Take over from manual control of ELSP (execlists) */ - guc_interrupts_capture(guc_to_gt(guc)); } void intel_guc_submission_disable(struct intel_guc *guc) @@ -735,8 +706,6 @@ void intel_guc_submission_disable(struct intel_guc *guc) /* Note: By the time we're here, GuC may have already been reset */ - guc_interrupts_release(gt); - guc_stage_desc_fini(guc); } -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-05-26 6:25 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-26 6:42 [PATCH 00/18] Non-interface changing GuC CTBs updates Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Non-interface changing GuC CTBs updates (rev2) Patchwork 2021-05-27 17:13 ` John Harrison 2021-05-27 17:09 ` Matthew Brost 2021-05-26 6:42 ` [PATCH 01/18] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 02/18] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` Matthew Brost [this message] 2021-05-26 6:42 ` [Intel-gfx] [PATCH 03/18] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost 2021-05-26 6:42 ` [PATCH 04/18] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 05/18] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 06/18] drm/i915/guc: Drop guc->interrupts.enabled Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-27 17:17 ` John Harrison 2021-05-27 17:17 ` John Harrison 2021-05-27 17:13 ` Matthew Brost 2021-05-27 17:13 ` Matthew Brost 2021-05-26 6:42 ` [PATCH 07/18] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 08/18] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 09/18] drm/i915/guc: Only rely on own CTB size Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 10/18] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 11/18] drm/i915/guc: Replace CTB array with explicit members Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 12/18] drm/i915/guc: Update sizes of CTB buffers Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 13/18] drm/i915/guc: Relax CTB response timeout Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 12:25 ` Michal Wajdeczko 2021-05-26 12:25 ` [Intel-gfx] " Michal Wajdeczko 2021-05-26 17:38 ` Matthew Brost 2021-05-26 17:38 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 14/18] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 15/18] drm/i915/guc: Ensure H2G buffer updates visible before tail update Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 12:36 ` Michal Wajdeczko 2021-05-26 12:36 ` [Intel-gfx] " Michal Wajdeczko 2021-05-26 17:58 ` Matthew Brost 2021-05-26 17:58 ` [Intel-gfx] " Matthew Brost 2021-05-28 1:13 ` John Harrison 2021-05-28 1:13 ` John Harrison 2021-05-28 6:52 ` Michal Wajdeczko 2021-05-28 6:52 ` Michal Wajdeczko 2021-05-26 6:42 ` [PATCH 16/18] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 17/18] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:42 ` [PATCH 18/18] drm/i915/guc: Always copy CT message to new allocation Matthew Brost 2021-05-26 6:42 ` [Intel-gfx] " Matthew Brost 2021-05-26 6:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Non-interface changing GuC CTBs updates (rev2) Patchwork 2021-05-27 17:13 ` John Harrison 2021-05-27 17:08 ` Matthew Brost 2021-05-26 7:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-05-26 9:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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