From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 19/31] cpu: Rename CPUClass vmsd -> legacy_vmsd
Date: Wed, 26 May 2021 16:46:58 -0700 [thread overview]
Message-ID: <20210526234710.125396-20-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210526234710.125396-1-richard.henderson@linaro.org>
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Quoting Peter Maydell [*]:
There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the
vmstate_cpu_common directly to handle the cpu-common fields,
and the cc->vmsd to handle the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).
See also commit b170fce3dd0 ("cpu: Register VMStateDescription
through CPUState") for historic background.
[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 5 +++--
cpu.c | 12 ++++++------
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/cpu.c | 3 +--
target/s390x/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
10 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d96ff4dace..1dfb788415 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -122,7 +122,8 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @vmsd: State description for migration.
+ * @legacy_vmsd: Legacy state description for migration.
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -177,7 +178,7 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *vmsd;
+ const VMStateDescription *legacy_vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/cpu.c b/cpu.c
index 6fe4af2797..c57f4c302b 100644
--- a/cpu.c
+++ b/cpu.c
@@ -143,13 +143,13 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#ifdef CONFIG_USER_ONLY
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
qdev_get_vmsd(DEVICE(cpu))->unmigratable);
- assert(cc->vmsd == NULL);
+ assert(cc->legacy_vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ if (cc->legacy_vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
@@ -159,10 +159,10 @@ void cpu_exec_unrealizefn(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
+ assert(cc->legacy_vmsd == NULL);
#else
- if (cc->vmsd != NULL) {
- vmstate_unregister(NULL, cc->vmsd, cpu);
+ if (cc->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7aeb4b1381..bf82276611 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1983,7 +1983,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->vmsd = &vmstate_arm_cpu;
+ cc->legacy_vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0f4596932b..37a8ebcc86 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->vmsd = &vms_avr_cpu;
+ cc->legacy_vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c496bfa1c2..5a1c8ead8e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6749,7 +6749,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->vmsd = &vmstate_x86_cpu;
+ cc->legacy_vmsd = &vmstate_x86_cpu;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 1ad2fe4aa3..eba56ac899 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -561,7 +561,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
+ cc->legacy_vmsd = &vmstate_mips_cpu;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 22ecbccad8..668fd141db 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9305,7 +9305,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
+ cc->legacy_vmsd = &vmstate_ppc_cpu;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3191fd0082..16510da259 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -638,8 +638,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- /* For now, mark unmigratable: */
- cc->vmsd = &vmstate_riscv_cpu;
+ cc->legacy_vmsd = &vmstate_riscv_cpu;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 64455cf309..7ce425f611 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -516,7 +516,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_s390_cpu;
+ cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
#endif
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc8..ba497561bf 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -889,7 +889,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_sparc_cpu;
+ cc->legacy_vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
--
2.25.1
next prev parent reply other threads:[~2021-05-27 0:18 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
2021-05-26 23:46 ` [PULL 01/31] exec/memory_ldst_cached: Sort declarations Richard Henderson
2021-05-26 23:46 ` [PULL 02/31] exec/memory_ldst_phys: " Richard Henderson
2021-05-26 23:46 ` [PULL 03/31] exec/memory_ldst: Use correct type sizes Richard Henderson
2021-05-26 23:46 ` [PULL 04/31] exec/memory_ldst_phys: " Richard Henderson
2021-05-26 23:46 ` [PULL 05/31] exec/memory_ldst_cached: Use correct type size Richard Henderson
2021-05-26 23:46 ` [PULL 06/31] exec/memory: " Richard Henderson
2021-05-26 23:46 ` [PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion Richard Henderson
2021-05-28 15:44 ` Philippe Mathieu-Daudé
2021-05-26 23:46 ` [PULL 08/31] accel/tcg: Keep TranslationBlock headers local to TCG Richard Henderson
2021-05-26 23:46 ` [PULL 09/31] replay: fix watchpoint processing for reverse debugging Richard Henderson
2021-05-26 23:46 ` [PULL 10/31] tcg/aarch64: Fix tcg_out_rotl Richard Henderson
2021-05-26 23:46 ` [PULL 11/31] cpu: Remove duplicated 'sysemu/hw_accel.h' header Richard Henderson
2021-05-26 23:46 ` [PULL 12/31] cpu: Split as cpu-common / cpu-sysemu Richard Henderson
2021-05-26 23:46 ` [PULL 13/31] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Richard Henderson
2021-05-26 23:46 ` [PULL 14/31] cpu: Introduce cpu_virtio_is_big_endian() Richard Henderson
2021-05-26 23:46 ` [PULL 15/31] cpu: Directly use cpu_write_elf*() fallback handlers in place Richard Henderson
2021-05-26 23:46 ` [PULL 16/31] cpu: Directly use get_paging_enabled() " Richard Henderson
2021-05-26 23:46 ` [PULL 17/31] cpu: Directly use get_memory_mapping() " Richard Henderson
2021-05-26 23:46 ` [PULL 18/31] cpu: Assert DeviceClass::vmsd is NULL on user emulation Richard Henderson
2021-05-26 23:46 ` Richard Henderson [this message]
2021-05-26 23:46 ` [PULL 20/31] cpu: Move AVR target vmsd field from CPUClass to DeviceClass Richard Henderson
2021-05-26 23:47 ` [PULL 21/31] cpu: Introduce SysemuCPUOps structure Richard Henderson
2021-05-26 23:47 ` [PULL 22/31] cpu: Move CPUClass::vmsd to SysemuCPUOps Richard Henderson
2021-05-26 23:47 ` [PULL 23/31] cpu: Move CPUClass::virtio_is_big_endian " Richard Henderson
2021-05-26 23:47 ` [PULL 24/31] cpu: Move CPUClass::get_crash_info " Richard Henderson
2021-05-26 23:47 ` [PULL 25/31] cpu: Move CPUClass::write_elf* " Richard Henderson
2021-05-26 23:47 ` [PULL 26/31] cpu: Move CPUClass::asidx_from_attrs " Richard Henderson
2021-05-26 23:47 ` [PULL 27/31] cpu: Move CPUClass::get_phys_page_debug " Richard Henderson
2021-05-26 23:47 ` [PULL 28/31] cpu: Move CPUClass::get_memory_mapping " Richard Henderson
2021-05-26 23:47 ` [PULL 29/31] cpu: Move CPUClass::get_paging_enabled " Richard Henderson
2021-05-26 23:47 ` [PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed Richard Henderson
2021-05-26 23:47 ` [PULL 31/31] hw/core: Constify TCGCPUOps Richard Henderson
2021-05-28 18:25 ` [PULL 00/31] tcg patch queue Peter Maydell
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