From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Abhinav Kumar <abhinavk@codeaurora.org>, Michael Turquette <mturquette@baylibre.com> Cc: Jonathan Marek <jonathan@marek.ca>, Stephen Boyd <sboyd@kernel.org>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Benjamin Li <benl@squareup.com> Subject: [RFC 2/8] drm/msm/dsi: save PLL registers across first PHY reset Date: Sat, 29 May 2021 03:25:02 +0300 [thread overview] Message-ID: <20210529002508.3839467-3-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20210529002508.3839467-1-dmitry.baryshkov@linaro.org> From: Benjamin Li <benl@squareup.com> Take advantage of previously-added support for persisting PLL registers across DSI PHY disable/enable cycles (see 328e1a6 'drm/msm/dsi: Save/Restore PLL status across PHY reset') to support persisting across the very first DSI PHY enable at boot. The bootloader may have left the PLL registers in a non-default state. For example, for dsi_pll_28nm.c on 8x16/8x39, the byte clock mux's power-on reset configuration is to bypass DIV1, but depending on bandwidth requirements[1] the bootloader may have set the DIV1 path. When the byte clock mux is registered with the generic clock framework at probe time, the framework reads & caches the value of the mux bit field (the initial clock parent). After PHY enable, when clk_set_rate is called on the byte clock, the framework assumes there is no need to reparent, and doesn't re-write the mux bit field. But PHY enable resets PLL registers, so the mux bit field actually silently reverted to the DIV1 bypass path. This causes the byte clock to be off by a factor of e.g. 2 for our tested WXGA panel. The above issue manifests as the display not working and a constant stream of FIFO/LP0 contention errors. [1] The specific requirement for triggering the DIV1 path (and thus this issue) on 28nm is a panel with pixel clock <116.7MHz (one-third the minimum VCO setting). FHD/1080p (~145MHz) is fine, WXGA/1280x800 (~75MHz) is not. Signed-off-by: Benjamin Li <benl@squareup.com> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 36878504bbb8..e5d25b44f8cb 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -738,6 +738,22 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) goto fail; } + /* + * As explained in msm_dsi_phy_enable, resetting the DSI PHY (as done + * in dsi_mgr_phy_enable) silently changes its PLL registers to power-on + * defaults, but the generic clock framework manages and caches several + * of the PLL registers. It initializes these caches at registration + * time via register read. + * + * As a result, we need to save DSI PLL registers once at probe in order + * for the first call to msm_dsi_phy_enable to successfully bring PLL + * registers back in line with what the generic clock framework expects. + * + * Subsequent PLL restores during msm_dsi_phy_enable will always be + * paired with PLL saves in msm_dsi_phy_disable. + */ + msm_dsi_phy_pll_save_state(phy); + dsi_phy_disable_resource(phy); platform_set_drvdata(pdev, phy); -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Abhinav Kumar <abhinavk@codeaurora.org>, Michael Turquette <mturquette@baylibre.com> Cc: Benjamin Li <benl@squareup.com>, Jonathan Marek <jonathan@marek.ca>, Stephen Boyd <sboyd@kernel.org>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie <airlied@linux.ie>, freedreno@lists.freedesktop.org Subject: [RFC 2/8] drm/msm/dsi: save PLL registers across first PHY reset Date: Sat, 29 May 2021 03:25:02 +0300 [thread overview] Message-ID: <20210529002508.3839467-3-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20210529002508.3839467-1-dmitry.baryshkov@linaro.org> From: Benjamin Li <benl@squareup.com> Take advantage of previously-added support for persisting PLL registers across DSI PHY disable/enable cycles (see 328e1a6 'drm/msm/dsi: Save/Restore PLL status across PHY reset') to support persisting across the very first DSI PHY enable at boot. The bootloader may have left the PLL registers in a non-default state. For example, for dsi_pll_28nm.c on 8x16/8x39, the byte clock mux's power-on reset configuration is to bypass DIV1, but depending on bandwidth requirements[1] the bootloader may have set the DIV1 path. When the byte clock mux is registered with the generic clock framework at probe time, the framework reads & caches the value of the mux bit field (the initial clock parent). After PHY enable, when clk_set_rate is called on the byte clock, the framework assumes there is no need to reparent, and doesn't re-write the mux bit field. But PHY enable resets PLL registers, so the mux bit field actually silently reverted to the DIV1 bypass path. This causes the byte clock to be off by a factor of e.g. 2 for our tested WXGA panel. The above issue manifests as the display not working and a constant stream of FIFO/LP0 contention errors. [1] The specific requirement for triggering the DIV1 path (and thus this issue) on 28nm is a panel with pixel clock <116.7MHz (one-third the minimum VCO setting). FHD/1080p (~145MHz) is fine, WXGA/1280x800 (~75MHz) is not. Signed-off-by: Benjamin Li <benl@squareup.com> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 36878504bbb8..e5d25b44f8cb 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -738,6 +738,22 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) goto fail; } + /* + * As explained in msm_dsi_phy_enable, resetting the DSI PHY (as done + * in dsi_mgr_phy_enable) silently changes its PLL registers to power-on + * defaults, but the generic clock framework manages and caches several + * of the PLL registers. It initializes these caches at registration + * time via register read. + * + * As a result, we need to save DSI PLL registers once at probe in order + * for the first call to msm_dsi_phy_enable to successfully bring PLL + * registers back in line with what the generic clock framework expects. + * + * Subsequent PLL restores during msm_dsi_phy_enable will always be + * paired with PLL saves in msm_dsi_phy_disable. + */ + msm_dsi_phy_pll_save_state(phy); + dsi_phy_disable_resource(phy); platform_set_drvdata(pdev, phy); -- 2.30.2
next prev parent reply other threads:[~2021-05-29 0:25 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-29 0:25 [RFC 0/8] drm/msm: split DSI PHY to generic PHY subsystem Dmitry Baryshkov 2021-05-29 0:25 ` Dmitry Baryshkov 2021-05-29 0:25 ` [RFC 1/8] drm/msm/dsi: make msm_dsi_phy_pll_restore_state static function Dmitry Baryshkov 2021-05-29 0:25 ` Dmitry Baryshkov 2021-05-29 0:25 ` Dmitry Baryshkov [this message] 2021-05-29 0:25 ` [RFC 2/8] drm/msm/dsi: save PLL registers across first PHY reset Dmitry Baryshkov 2021-05-29 0:25 ` [RFC 3/8] drm/msm/dsi: drop msm_dsi_phy_pll_save_state from 7nm and 10nm drivers Dmitry Baryshkov 2021-05-29 0:25 ` Dmitry Baryshkov 2021-05-29 0:25 ` [RFC 4/8] drm/msm/dsi: move msm_dsi_phy_pll_save_state call to msm_dsi_phy_disable Dmitry Baryshkov 2021-05-29 0:25 ` Dmitry Baryshkov 2021-05-29 0:25 ` [RFC 5/8] lib: add small API for handling register snapshots Dmitry Baryshkov 2021-05-29 0:25 ` Dmitry Baryshkov 2021-06-03 14:45 ` Rob Clark 2021-06-03 14:45 ` Rob Clark 2021-06-03 16:33 ` Dmitry Baryshkov 2021-06-03 16:33 ` Dmitry Baryshkov 2021-06-08 17:04 ` Rob Clark 2021-06-08 17:04 ` Rob Clark 2021-05-29 0:25 ` [RFC 6/8] drm/msm: port msm_disp_snapshot to dump_state Dmitry Baryshkov 2021-05-29 0:25 ` Dmitry Baryshkov 2021-05-29 0:25 ` [RFC 7/8] drm/msm: do include unused headers in msm_disp_snapshot.h Dmitry Baryshkov 2021-05-29 0:25 ` Dmitry Baryshkov 2021-05-29 0:25 ` [RFC 8/8] drm/msm: split DSI PHY driver to generic phy subsystem Dmitry Baryshkov
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