From: Uma Shankar <uma.shankar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Uma Shankar <uma.shankar@intel.com>, bhanuprakash.modem@intel.com Subject: [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout Date: Tue, 1 Jun 2021 16:11:35 +0530 [thread overview] Message-ID: <20210601104135.29020-10-uma.shankar@intel.com> (raw) In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> Enable support for Logarithmic gamma readout for XE_LPD. Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 72 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++ 2 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a8b771f22880..1238fe05b358 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -486,6 +486,17 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw); } +static void d13_lut_logarithmic_pack(struct drm_color_lut *entry, + u32 ldw, u32 udw) +{ + entry->red = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_LDW_MASK, ldw); + entry->green = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK, ldw); + entry->blue = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK, ldw); +} + static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -2434,6 +2445,66 @@ static void d13_load_luts(const struct intel_crtc_state *crtc_state) intel_dsb_commit(crtc_state); } +static struct drm_property_blob * +d13_read_lut_logarithmic(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + u32 gamma_max_val = 0xFFFF; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_lut) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT); + + for (i = 0; i < lut_size - 3; i++) { + u32 ldw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + u32 udw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + + d13_lut_logarithmic_pack(&lut[i], ldw, udw); + } + + /* All the extended ranges are now limited to last value of 1.0 */ + while (i < lut_size) { + lut[i].red = gamma_max_val; + lut[i].green = gamma_max_val; + lut[i].blue = gamma_max_val; + i++; + }; + + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); + + return blob; +} + +static void d13_read_luts(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) + return; + + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { + case GAMMA_MODE_MODE_8BIT: + crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_12BIT_LOGARITHMIC: + crtc_state->hw.gamma_lut = d13_read_lut_logarithmic(crtc); + break; + default: + crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); + } +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -2488,6 +2559,7 @@ void intel_color_init(struct intel_crtc *crtc) if (DISPLAY_VER(dev_priv) >= 13) { dev_priv->display.load_luts = d13_load_luts; + dev_priv->display.read_luts = d13_read_luts; } else if (DISPLAY_VER(dev_priv) >= 11) { dev_priv->display.load_luts = icl_load_luts; dev_priv->display.read_luts = icl_read_luts; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 957f97edf035..dc10b5e2ff3c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7750,6 +7750,12 @@ enum { #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ #define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */ +#define PAL_PREC_LOGARITHMIC_RED_LDW_MASK REG_GENMASK(29, 24) +#define PAL_PREC_LOGARITHMIC_RED_UDW_MASK REG_GENMASK(29, 20) +#define PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK REG_GENMASK(19, 14) +#define PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK REG_GENMASK(19, 10) +#define PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK REG_GENMASK(9, 4) +#define PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK REG_GENMASK(9, 0) /* DMC */ #define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4) -- 2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Uma Shankar <uma.shankar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout Date: Tue, 1 Jun 2021 16:11:35 +0530 [thread overview] Message-ID: <20210601104135.29020-10-uma.shankar@intel.com> (raw) In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> Enable support for Logarithmic gamma readout for XE_LPD. Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 72 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++ 2 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a8b771f22880..1238fe05b358 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -486,6 +486,17 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw); } +static void d13_lut_logarithmic_pack(struct drm_color_lut *entry, + u32 ldw, u32 udw) +{ + entry->red = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_LDW_MASK, ldw); + entry->green = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK, ldw); + entry->blue = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK, ldw); +} + static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -2434,6 +2445,66 @@ static void d13_load_luts(const struct intel_crtc_state *crtc_state) intel_dsb_commit(crtc_state); } +static struct drm_property_blob * +d13_read_lut_logarithmic(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + u32 gamma_max_val = 0xFFFF; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_lut) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT); + + for (i = 0; i < lut_size - 3; i++) { + u32 ldw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + u32 udw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + + d13_lut_logarithmic_pack(&lut[i], ldw, udw); + } + + /* All the extended ranges are now limited to last value of 1.0 */ + while (i < lut_size) { + lut[i].red = gamma_max_val; + lut[i].green = gamma_max_val; + lut[i].blue = gamma_max_val; + i++; + }; + + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); + + return blob; +} + +static void d13_read_luts(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) + return; + + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { + case GAMMA_MODE_MODE_8BIT: + crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_12BIT_LOGARITHMIC: + crtc_state->hw.gamma_lut = d13_read_lut_logarithmic(crtc); + break; + default: + crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); + } +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -2488,6 +2559,7 @@ void intel_color_init(struct intel_crtc *crtc) if (DISPLAY_VER(dev_priv) >= 13) { dev_priv->display.load_luts = d13_load_luts; + dev_priv->display.read_luts = d13_read_luts; } else if (DISPLAY_VER(dev_priv) >= 11) { dev_priv->display.load_luts = icl_load_luts; dev_priv->display.read_luts = icl_read_luts; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 957f97edf035..dc10b5e2ff3c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7750,6 +7750,12 @@ enum { #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ #define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */ +#define PAL_PREC_LOGARITHMIC_RED_LDW_MASK REG_GENMASK(29, 24) +#define PAL_PREC_LOGARITHMIC_RED_UDW_MASK REG_GENMASK(29, 20) +#define PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK REG_GENMASK(19, 14) +#define PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK REG_GENMASK(19, 10) +#define PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK REG_GENMASK(9, 4) +#define PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK REG_GENMASK(9, 0) /* DMC */ #define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4) -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-01 10:06 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-01 10:41 [PATCH 0/9] Enhance pipe color support for multi segmented luts Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:41 ` [PATCH 1/9] drm: Add gamma mode property Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-02 9:09 ` Pekka Paalanen 2021-06-02 9:09 ` [Intel-gfx] " Pekka Paalanen 2021-06-02 20:18 ` Shankar, Uma 2021-06-02 20:18 ` [Intel-gfx] " Shankar, Uma 2021-06-03 8:05 ` Pekka Paalanen 2021-06-03 8:05 ` [Intel-gfx] " Pekka Paalanen 2021-06-01 10:41 ` [PATCH 2/9] drm/i915/xelpd: Define color lut range structure Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:41 ` [PATCH 3/9] drm/i915/xelpd: Add support for Logarithmic gamma mode Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:41 ` [PATCH 4/9] drm/i915/xelpd: Attach gamma mode property Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:41 ` [PATCH 5/9] drm: Add Client Cap for advance gamma mode Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-02 2:53 ` kernel test robot 2021-06-02 2:53 ` kernel test robot 2021-06-02 2:53 ` [Intel-gfx] " kernel test robot 2021-06-02 9:03 ` Pekka Paalanen 2021-06-02 9:03 ` [Intel-gfx] " Pekka Paalanen 2021-06-02 20:08 ` Shankar, Uma 2021-06-02 20:08 ` [Intel-gfx] " Shankar, Uma 2021-06-01 10:41 ` [PATCH 6/9] drm/i915/xelpd: logarithmic gamma enabled only with " Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:41 ` [PATCH 7/9] drm/i915/xelpd: Enable Pipe Degamma Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:41 ` [PATCH 8/9] drm/i915/xelpd: Add Pipe Color Lut caps to platform config Uma Shankar 2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:41 ` Uma Shankar [this message] 2021-06-01 10:41 ` [Intel-gfx] [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout Uma Shankar 2021-06-01 12:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enhance pipe color support for multi segmented luts Patchwork 2021-06-01 13:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-06-01 17:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-06-04 18:51 ` [PATCH 0/9] " Harry Wentland 2021-06-04 18:51 ` [Intel-gfx] " Harry Wentland 2021-06-07 7:29 ` Pekka Paalanen 2021-06-07 7:29 ` [Intel-gfx] " Pekka Paalanen 2021-06-07 18:07 ` Shankar, Uma 2021-06-07 18:07 ` [Intel-gfx] " Shankar, Uma 2021-06-08 7:59 ` Pekka Paalanen 2021-06-08 7:59 ` [Intel-gfx] " Pekka Paalanen 2021-06-07 18:01 ` Shankar, Uma 2021-06-07 18:01 ` [Intel-gfx] " Shankar, Uma 2021-06-07 21:00 ` Harry Wentland 2021-06-07 21:00 ` [Intel-gfx] " Harry Wentland
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