From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Uma Shankar <uma.shankar@intel.com>, bhanuprakash.modem@intel.com
Subject: [PATCH 15/21] drm/i915/xelpd: Enable Plane CSC
Date: Tue, 1 Jun 2021 16:22:12 +0530 [thread overview]
Message-ID: <20210601105218.29185-16-uma.shankar@intel.com> (raw)
In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com>
Implement plane CSC for ICL+
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 5 +-
drivers/gpu/drm/i915/display/intel_color.c | 82 +++++++++++++++++++
.../drm/i915/display/skl_universal_plane.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 5de9c98beaf6..ec7646790892 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -499,6 +499,7 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct skl_ddb_entry entries_y[I915_MAX_PLANES];
struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 update_mask = new_crtc_state->update_planes;
struct intel_plane *plane;
@@ -513,8 +514,10 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
- if (new_plane_state->uapi.color_mgmt_changed)
+ if (new_plane_state->uapi.color_mgmt_changed) {
intel_color_load_plane_luts(&new_plane_state->uapi);
+ dev_priv->display.load_plane_csc_matrix(&new_plane_state->uapi);
+ }
if (new_plane_state->uapi.visible ||
new_plane_state->planar_slave) {
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 6d57a47d8a60..8b4f653b213d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2119,6 +2119,83 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
}
}
+static void icl_load_plane_csc_matrix(const struct drm_plane_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ u16 coeffs[9] = {};
+ u16 postoff = 0;
+ int i;
+
+ if (!icl_is_hdr_plane(dev_priv, plane) || !state->ctm)
+ return;
+
+ ctm = state->ctm->data;
+ input = ctm->matrix;
+
+ /*
+ * Convert fixed point S31.32 input to format supported by the
+ * hardware.
+ */
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+ u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
+
+ /*
+ * Clamp input value to min/max supported by
+ * hardware.
+ */
+ abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+ /* sign bit */
+ if (CTM_COEFF_NEGATIVE(input[i]))
+ coeffs[i] |= 1 << 15;
+
+ if (abs_coeff < CTM_COEFF_0_125)
+ coeffs[i] |= (3 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 12);
+ else if (abs_coeff < CTM_COEFF_0_25)
+ coeffs[i] |= (2 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 11);
+ else if (abs_coeff < CTM_COEFF_0_5)
+ coeffs[i] |= (1 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 10);
+ else if (abs_coeff < CTM_COEFF_1_0)
+ coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
+ else if (abs_coeff < CTM_COEFF_2_0)
+ coeffs[i] |= (7 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 8);
+ else
+ coeffs[i] |= (6 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 7);
+ }
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0),
+ coeffs[0] << 16 | coeffs[1]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1),
+ coeffs[2] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2),
+ coeffs[3] << 16 | coeffs[4]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3),
+ coeffs[5] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4),
+ coeffs[6] << 16 | coeffs[7]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5),
+ coeffs[8] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
/* FIXME input bpc? */
static const struct drm_color_lut_range d13_degamma_hdr[] = {
/* segment 1 */
@@ -2343,7 +2420,12 @@ int intel_plane_color_init(struct drm_plane *plane)
LUT_TYPE_DEGAMMA);
dev_priv->display.load_plane_luts = d13_plane_load_luts;
+ dev_priv->display.load_plane_csc_matrix = icl_load_plane_csc_matrix;
+
drm_plane_attach_degamma_properties(plane);
+
+ if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id))
+ drm_plane_attach_ctm_property(plane);
}
return ret;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index aadb984fdf77..6ba670b6a5c9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -965,6 +965,10 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
if (plane_state->uapi.degamma_lut)
plane_color_ctl |= PLANE_PRE_CSC_GAMMA_ENABLE;
+ /* FIXME needs hw.ctm */
+ if (plane_state->uapi.ctm)
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df8500a86e9d..a8e35357aea0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7187,6 +7187,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_PRE_CSC_GAMMA_ENABLE (1 << 14)
--
2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 15/21] drm/i915/xelpd: Enable Plane CSC
Date: Tue, 1 Jun 2021 16:22:12 +0530 [thread overview]
Message-ID: <20210601105218.29185-16-uma.shankar@intel.com> (raw)
In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com>
Implement plane CSC for ICL+
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 5 +-
drivers/gpu/drm/i915/display/intel_color.c | 82 +++++++++++++++++++
.../drm/i915/display/skl_universal_plane.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 5de9c98beaf6..ec7646790892 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -499,6 +499,7 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct skl_ddb_entry entries_y[I915_MAX_PLANES];
struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 update_mask = new_crtc_state->update_planes;
struct intel_plane *plane;
@@ -513,8 +514,10 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
- if (new_plane_state->uapi.color_mgmt_changed)
+ if (new_plane_state->uapi.color_mgmt_changed) {
intel_color_load_plane_luts(&new_plane_state->uapi);
+ dev_priv->display.load_plane_csc_matrix(&new_plane_state->uapi);
+ }
if (new_plane_state->uapi.visible ||
new_plane_state->planar_slave) {
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 6d57a47d8a60..8b4f653b213d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2119,6 +2119,83 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
}
}
+static void icl_load_plane_csc_matrix(const struct drm_plane_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ u16 coeffs[9] = {};
+ u16 postoff = 0;
+ int i;
+
+ if (!icl_is_hdr_plane(dev_priv, plane) || !state->ctm)
+ return;
+
+ ctm = state->ctm->data;
+ input = ctm->matrix;
+
+ /*
+ * Convert fixed point S31.32 input to format supported by the
+ * hardware.
+ */
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+ u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
+
+ /*
+ * Clamp input value to min/max supported by
+ * hardware.
+ */
+ abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+ /* sign bit */
+ if (CTM_COEFF_NEGATIVE(input[i]))
+ coeffs[i] |= 1 << 15;
+
+ if (abs_coeff < CTM_COEFF_0_125)
+ coeffs[i] |= (3 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 12);
+ else if (abs_coeff < CTM_COEFF_0_25)
+ coeffs[i] |= (2 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 11);
+ else if (abs_coeff < CTM_COEFF_0_5)
+ coeffs[i] |= (1 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 10);
+ else if (abs_coeff < CTM_COEFF_1_0)
+ coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
+ else if (abs_coeff < CTM_COEFF_2_0)
+ coeffs[i] |= (7 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 8);
+ else
+ coeffs[i] |= (6 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 7);
+ }
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0),
+ coeffs[0] << 16 | coeffs[1]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1),
+ coeffs[2] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2),
+ coeffs[3] << 16 | coeffs[4]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3),
+ coeffs[5] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4),
+ coeffs[6] << 16 | coeffs[7]);
+ intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5),
+ coeffs[8] << 16);
+
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
/* FIXME input bpc? */
static const struct drm_color_lut_range d13_degamma_hdr[] = {
/* segment 1 */
@@ -2343,7 +2420,12 @@ int intel_plane_color_init(struct drm_plane *plane)
LUT_TYPE_DEGAMMA);
dev_priv->display.load_plane_luts = d13_plane_load_luts;
+ dev_priv->display.load_plane_csc_matrix = icl_load_plane_csc_matrix;
+
drm_plane_attach_degamma_properties(plane);
+
+ if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id))
+ drm_plane_attach_ctm_property(plane);
}
return ret;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index aadb984fdf77..6ba670b6a5c9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -965,6 +965,10 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
if (plane_state->uapi.degamma_lut)
plane_color_ctl |= PLANE_PRE_CSC_GAMMA_ENABLE;
+ /* FIXME needs hw.ctm */
+ if (plane_state->uapi.ctm)
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df8500a86e9d..a8e35357aea0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7187,6 +7187,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_PRE_CSC_GAMMA_ENABLE (1 << 14)
--
2.26.2
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next prev parent reply other threads:[~2021-06-01 10:16 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-01 10:51 [PATCH 00/21] Add Support for Plane Color Lut and CSC features Uma Shankar
2021-06-01 10:51 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:51 ` [PATCH 01/21] drm: Add Enhanced Gamma and color lut range attributes Uma Shankar
2021-06-01 10:51 ` [Intel-gfx] " Uma Shankar
2021-06-02 9:33 ` Pekka Paalanen
2021-06-02 9:33 ` [Intel-gfx] " Pekka Paalanen
2021-06-02 20:26 ` Shankar, Uma
2021-06-02 20:26 ` [Intel-gfx] " Shankar, Uma
2021-06-04 15:23 ` Harry Wentland
2021-06-04 15:23 ` [Intel-gfx] " Harry Wentland
2021-06-07 17:19 ` Shankar, Uma
2021-06-07 17:19 ` [Intel-gfx] " Shankar, Uma
2021-06-01 10:51 ` [PATCH 02/21] drm: Add Plane Degamma Mode property Uma Shankar
2021-06-01 10:51 ` [Intel-gfx] " Uma Shankar
2021-06-04 18:24 ` Harry Wentland
2021-06-04 18:24 ` [Intel-gfx] " Harry Wentland
2021-06-07 11:00 ` Pekka Paalanen
2021-06-07 11:00 ` [Intel-gfx] " Pekka Paalanen
2021-06-07 17:34 ` Shankar, Uma
2021-06-07 17:34 ` [Intel-gfx] " Shankar, Uma
2021-06-08 8:34 ` Pekka Paalanen
2021-06-08 8:34 ` [Intel-gfx] " Pekka Paalanen
2021-06-01 10:52 ` [PATCH 03/21] drm: Add Plane Degamma Lut property Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 04/21] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-28 15:14 ` Harry Wentland
2021-06-28 15:14 ` [Intel-gfx] " Harry Wentland
2021-06-30 11:36 ` Shankar, Uma
2021-06-30 11:36 ` [Intel-gfx] " Shankar, Uma
2021-06-01 10:52 ` [PATCH 05/21] drm/i915/xelpd: Add register definitions for Plane Degamma Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 06/21] drm/i915/xelpd: Enable plane color features Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 07/21] drm/i915/xelpd: Add color capabilities of SDR planes Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 08/21] drm/i915/xelpd: Program Plane Degamma Registers Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 09/21] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 10/21] drm/i915/xelpd: Initialize plane color features Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 11/21] drm/i915/xelpd: Load plane color luts from atomic flip Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 12/21] drm: Add Plane CTM property Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 13/21] drm: Add helper to attach Plane ctm property Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 14/21] drm/i915/xelpd: Define Plane CSC Registers Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` Uma Shankar [this message]
2021-06-01 10:52 ` [Intel-gfx] [PATCH 15/21] drm/i915/xelpd: Enable Plane CSC Uma Shankar
2021-06-01 10:52 ` [PATCH 16/21] drm: Add Plane Gamma Mode property Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 17/21] drm: Add Plane Gamma Lut property Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 18/21] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 19/21] drm/i915/xelpd: Add register definitions for Plane Gamma Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 20/21] drm/i915/xelpd: Program Plane Gamma Registers Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 10:52 ` [PATCH 21/21] drm/i915/xelpd: Enable plane gamma Uma Shankar
2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar
2021-06-01 13:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Support for Plane Color Lut and CSC features Patchwork
2021-06-01 13:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-01 13:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-06-02 9:28 ` [PATCH 00/21] " Pekka Paalanen
2021-06-02 9:28 ` [Intel-gfx] " Pekka Paalanen
2021-06-02 20:22 ` Shankar, Uma
2021-06-02 20:22 ` [Intel-gfx] " Shankar, Uma
2021-06-02 23:42 ` Harry Wentland
2021-06-02 23:42 ` [Intel-gfx] " Harry Wentland
2021-06-03 8:47 ` Pekka Paalanen
2021-06-03 8:47 ` [Intel-gfx] " Pekka Paalanen
2021-06-03 12:30 ` Sebastian Wick
2021-06-03 12:30 ` [Intel-gfx] " Sebastian Wick
2021-06-03 12:58 ` Pekka Paalanen
2021-06-03 12:58 ` [Intel-gfx] " Pekka Paalanen
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