[PATCH] arm: dts: k3-j7200: ddr: Update to 0.5.0 version of DDR for LPDDR 2666MTs

[<praneeth@ti.com>]

From: Kevin Scholz <k-scholz@ti.com>

Update the ddr settings to use the DDR reg config tool rev 0.5.0.
This enables 2666MTs LPDDR configuration on J7200.

Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
---
 ...00.dtsi => k3-j7200-ddr-evm-lp4-2666.dtsi} | 437 +++++++++---------
 .../arm/dts/k3-j7200-r5-common-proc-board.dts |   2 +-
 2 files changed, 220 insertions(+), 219 deletions(-)
 rename arch/arm/dts/{k3-j7200-ddr-evm-lp4-1600.dtsi => k3-j7200-ddr-evm-lp4-2666.dtsi} (90%)

diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
similarity index 90%
rename from arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
rename to arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
index 12ffd913d1..42ac8c5c89 100644
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
@@ -1,13 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.3.0
- * This file was generated on 06/08/2020
- * Includes hand edits
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
+ * This file was generated on 08/07/2020
+ * Includes hand-edits
  */
 
 #define DDRSS_PLL_FHS_CNT 10
-#define DDRSS_PLL_FREQUENCY_1 400000000
-#define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_PLL_FREQUENCY_1 666500000
+#define DDRSS_PLL_FREQUENCY_2 666500000
 
 #define DDRSS_CTL_00_DATA 0x00000B00
 #define DDRSS_CTL_01_DATA 0x00000000
@@ -20,14 +21,14 @@
 #define DDRSS_CTL_08_DATA 0x000186A0
 #define DDRSS_CTL_09_DATA 0x00000005
 #define DDRSS_CTL_10_DATA 0x00000064
-#define DDRSS_CTL_11_DATA 0x00027100
-#define DDRSS_CTL_12_DATA 0x00186A00
+#define DDRSS_CTL_11_DATA 0x000411AB
+#define DDRSS_CTL_12_DATA 0x0028B0AB
 #define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000640
-#define DDRSS_CTL_15_DATA 0x00027100
-#define DDRSS_CTL_16_DATA 0x00186A00
+#define DDRSS_CTL_14_DATA 0x00000A6B
+#define DDRSS_CTL_15_DATA 0x000411AB
+#define DDRSS_CTL_16_DATA 0x0028B0AB
 #define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000640
+#define DDRSS_CTL_18_DATA 0x00000A6B
 #define DDRSS_CTL_19_DATA 0x01010000
 #define DDRSS_CTL_20_DATA 0x02011001
 #define DDRSS_CTL_21_DATA 0x02010000
@@ -37,66 +38,66 @@
 #define DDRSS_CTL_25_DATA 0x00000000
 #define DDRSS_CTL_26_DATA 0x00000000
 #define DDRSS_CTL_27_DATA 0x02020200
-#define DDRSS_CTL_28_DATA 0x00002020
+#define DDRSS_CTL_28_DATA 0x00003636
 #define DDRSS_CTL_29_DATA 0x00100000
 #define DDRSS_CTL_30_DATA 0x00000000
 #define DDRSS_CTL_31_DATA 0x00000000
 #define DDRSS_CTL_32_DATA 0x00000000
 #define DDRSS_CTL_33_DATA 0x00000000
 #define DDRSS_CTL_34_DATA 0x040C0000
-#define DDRSS_CTL_35_DATA 0x081C081C
+#define DDRSS_CTL_35_DATA 0x0C300C30
 #define DDRSS_CTL_36_DATA 0x00050804
 #define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x08000204
-#define DDRSS_CTL_39_DATA 0x0B240034
-#define DDRSS_CTL_40_DATA 0x08001910
-#define DDRSS_CTL_41_DATA 0x0B240034
-#define DDRSS_CTL_42_DATA 0x20001910
+#define DDRSS_CTL_38_DATA 0x0D000204
+#define DDRSS_CTL_39_DATA 0x113C0057
+#define DDRSS_CTL_40_DATA 0x0D00291B
+#define DDRSS_CTL_41_DATA 0x113C0057
+#define DDRSS_CTL_42_DATA 0x2000291B
 #define DDRSS_CTL_43_DATA 0x000A0A09
 #define DDRSS_CTL_44_DATA 0x040006DB
-#define DDRSS_CTL_45_DATA 0x0C0A0904
-#define DDRSS_CTL_46_DATA 0x06006DB0
-#define DDRSS_CTL_47_DATA 0x0C0A0906
-#define DDRSS_CTL_48_DATA 0x06006DB0
-#define DDRSS_CTL_49_DATA 0x02030406
-#define DDRSS_CTL_50_DATA 0x11040500
-#define DDRSS_CTL_51_DATA 0x08121112
+#define DDRSS_CTL_45_DATA 0x130E0B04
+#define DDRSS_CTL_46_DATA 0x0A00B6D0
+#define DDRSS_CTL_47_DATA 0x130E0B0A
+#define DDRSS_CTL_48_DATA 0x0A00B6D0
+#define DDRSS_CTL_49_DATA 0x0203040A
+#define DDRSS_CTL_50_DATA 0x1C040500
+#define DDRSS_CTL_51_DATA 0x081D1C1D
 #define DDRSS_CTL_52_DATA 0x14000D0A
 #define DDRSS_CTL_53_DATA 0x02010A0A
 #define DDRSS_CTL_54_DATA 0x01010002
-#define DDRSS_CTL_55_DATA 0x04222208
-#define DDRSS_CTL_56_DATA 0x04131304
-#define DDRSS_CTL_57_DATA 0x00001313
+#define DDRSS_CTL_55_DATA 0x04383808
+#define DDRSS_CTL_56_DATA 0x041F1F04
+#define DDRSS_CTL_57_DATA 0x00001F1F
 #define DDRSS_CTL_58_DATA 0x00010100
 #define DDRSS_CTL_59_DATA 0x03010000
 #define DDRSS_CTL_60_DATA 0x00000E08
 #define DDRSS_CTL_61_DATA 0x000000BB
-#define DDRSS_CTL_62_DATA 0x000000E0
-#define DDRSS_CTL_63_DATA 0x00000C28
-#define DDRSS_CTL_64_DATA 0x000000E0
-#define DDRSS_CTL_65_DATA 0x00000C28
+#define DDRSS_CTL_62_DATA 0x00000176
+#define DDRSS_CTL_63_DATA 0x00001448
+#define DDRSS_CTL_64_DATA 0x00000176
+#define DDRSS_CTL_65_DATA 0x00001448
 #define DDRSS_CTL_66_DATA 0x00000005
 #define DDRSS_CTL_67_DATA 0x00030000
-#define DDRSS_CTL_68_DATA 0x00380010
-#define DDRSS_CTL_69_DATA 0x0038017E
-#define DDRSS_CTL_70_DATA 0x0040017E
+#define DDRSS_CTL_68_DATA 0x005D0010
+#define DDRSS_CTL_69_DATA 0x005D0282
+#define DDRSS_CTL_70_DATA 0x00400282
 #define DDRSS_CTL_71_DATA 0x00120103
-#define DDRSS_CTL_72_DATA 0x00060005
-#define DDRSS_CTL_73_DATA 0x14080006
-#define DDRSS_CTL_74_DATA 0x05050114
-#define DDRSS_CTL_75_DATA 0x0201030A
-#define DDRSS_CTL_76_DATA 0x030C0605
-#define DDRSS_CTL_77_DATA 0x06050201
-#define DDRSS_CTL_78_DATA 0x0001030C
+#define DDRSS_CTL_72_DATA 0x000A0005
+#define DDRSS_CTL_73_DATA 0x1F08000A
+#define DDRSS_CTL_74_DATA 0x0505011F
+#define DDRSS_CTL_75_DATA 0x0301030A
+#define DDRSS_CTL_76_DATA 0x03130A07
+#define DDRSS_CTL_77_DATA 0x0A070301
+#define DDRSS_CTL_78_DATA 0x00010313
 #define DDRSS_CTL_79_DATA 0x000F000F
-#define DDRSS_CTL_80_DATA 0x00E600E6
-#define DDRSS_CTL_81_DATA 0x00E600E6
+#define DDRSS_CTL_80_DATA 0x01800180
+#define DDRSS_CTL_81_DATA 0x01800180
 #define DDRSS_CTL_82_DATA 0x03050505
 #define DDRSS_CTL_83_DATA 0x03010303
-#define DDRSS_CTL_84_DATA 0x0C050605
-#define DDRSS_CTL_85_DATA 0x03020603
-#define DDRSS_CTL_86_DATA 0x0C050605
-#define DDRSS_CTL_87_DATA 0x03020603
+#define DDRSS_CTL_84_DATA 0x14070A07
+#define DDRSS_CTL_85_DATA 0x03030A03
+#define DDRSS_CTL_86_DATA 0x14070A07
+#define DDRSS_CTL_87_DATA 0x03030A03
 #define DDRSS_CTL_88_DATA 0x03010000
 #define DDRSS_CTL_89_DATA 0x00010000
 #define DDRSS_CTL_90_DATA 0x00000000
@@ -118,20 +119,20 @@
 #define DDRSS_CTL_106_DATA 0x00002EC0
 #define DDRSS_CTL_107_DATA 0x00000000
 #define DDRSS_CTL_108_DATA 0x0000051D
-#define DDRSS_CTL_109_DATA 0x00030A00
-#define DDRSS_CTL_110_DATA 0x00030A00
-#define DDRSS_CTL_111_DATA 0x00030A00
-#define DDRSS_CTL_112_DATA 0x00030A00
-#define DDRSS_CTL_113_DATA 0x00030A00
+#define DDRSS_CTL_109_DATA 0x00051200
+#define DDRSS_CTL_110_DATA 0x00051200
+#define DDRSS_CTL_111_DATA 0x00051200
+#define DDRSS_CTL_112_DATA 0x00051200
+#define DDRSS_CTL_113_DATA 0x00051200
 #define DDRSS_CTL_114_DATA 0x00000000
-#define DDRSS_CTL_115_DATA 0x00005518
-#define DDRSS_CTL_116_DATA 0x00030A00
-#define DDRSS_CTL_117_DATA 0x00030A00
-#define DDRSS_CTL_118_DATA 0x00030A00
-#define DDRSS_CTL_119_DATA 0x00030A00
-#define DDRSS_CTL_120_DATA 0x00030A00
+#define DDRSS_CTL_115_DATA 0x00008DF8
+#define DDRSS_CTL_116_DATA 0x00051200
+#define DDRSS_CTL_117_DATA 0x00051200
+#define DDRSS_CTL_118_DATA 0x00051200
+#define DDRSS_CTL_119_DATA 0x00051200
+#define DDRSS_CTL_120_DATA 0x00051200
 #define DDRSS_CTL_121_DATA 0x00000000
-#define DDRSS_CTL_122_DATA 0x00005518
+#define DDRSS_CTL_122_DATA 0x00008DF8
 #define DDRSS_CTL_123_DATA 0x00000000
 #define DDRSS_CTL_124_DATA 0x00000000
 #define DDRSS_CTL_125_DATA 0x00000000
@@ -140,8 +141,8 @@
 #define DDRSS_CTL_128_DATA 0x00000000
 #define DDRSS_CTL_129_DATA 0x00000000
 #define DDRSS_CTL_130_DATA 0x00000000
-#define DDRSS_CTL_131_DATA 0x05030500
-#define DDRSS_CTL_132_DATA 0x00030503
+#define DDRSS_CTL_131_DATA 0x07030500
+#define DDRSS_CTL_132_DATA 0x00030703
 #define DDRSS_CTL_133_DATA 0x0A090000
 #define DDRSS_CTL_134_DATA 0x0A090701
 #define DDRSS_CTL_135_DATA 0x0900000E
@@ -176,23 +177,23 @@
 #define DDRSS_CTL_164_DATA 0x000A0000
 #define DDRSS_CTL_165_DATA 0x000D0005
 #define DDRSS_CTL_166_DATA 0x000D0404
-#define DDRSS_CTL_167_DATA 0x005000A0
-#define DDRSS_CTL_168_DATA 0x060600C8
-#define DDRSS_CTL_169_DATA 0x00A000C8
-#define DDRSS_CTL_170_DATA 0x00C80050
-#define DDRSS_CTL_171_DATA 0x00C80606
+#define DDRSS_CTL_167_DATA 0x0086010B
+#define DDRSS_CTL_168_DATA 0x0A0A014E
+#define DDRSS_CTL_169_DATA 0x010B014E
+#define DDRSS_CTL_170_DATA 0x014E0086
+#define DDRSS_CTL_171_DATA 0x014E0A0A
 #define DDRSS_CTL_172_DATA 0x00000000
 #define DDRSS_CTL_173_DATA 0x00000000
 #define DDRSS_CTL_174_DATA 0x00000000
-#define DDRSS_CTL_175_DATA 0x12A40084
-#define DDRSS_CTL_176_DATA 0x2B0012A4
+#define DDRSS_CTL_175_DATA 0x24C40084
+#define DDRSS_CTL_176_DATA 0x2B0024C4
 #define DDRSS_CTL_177_DATA 0x00002B2B
 #define DDRSS_CTL_178_DATA 0x36000000
 #define DDRSS_CTL_179_DATA 0x27270036
 #define DDRSS_CTL_180_DATA 0x0F0F0000
 #define DDRSS_CTL_181_DATA 0x00000000
 #define DDRSS_CTL_182_DATA 0x00841515
-#define DDRSS_CTL_183_DATA 0x12A412A4
+#define DDRSS_CTL_183_DATA 0x24C424C4
 #define DDRSS_CTL_184_DATA 0x2B2B2B00
 #define DDRSS_CTL_185_DATA 0x00000000
 #define DDRSS_CTL_186_DATA 0x00363600
@@ -270,12 +271,12 @@
 #define DDRSS_CTL_258_DATA 0x00320040
 #define DDRSS_CTL_259_DATA 0x00020008
 #define DDRSS_CTL_260_DATA 0x00400100
-#define DDRSS_CTL_261_DATA 0x00180320
+#define DDRSS_CTL_261_DATA 0x00280536
 #define DDRSS_CTL_262_DATA 0x01000200
-#define DDRSS_CTL_263_DATA 0x03200040
-#define DDRSS_CTL_264_DATA 0x00000018
-#define DDRSS_CTL_265_DATA 0x00280003
-#define DDRSS_CTL_266_DATA 0x01000028
+#define DDRSS_CTL_263_DATA 0x05360040
+#define DDRSS_CTL_264_DATA 0x00000028
+#define DDRSS_CTL_265_DATA 0x00430003
+#define DDRSS_CTL_266_DATA 0x01000043
 #define DDRSS_CTL_267_DATA 0x00000000
 #define DDRSS_CTL_268_DATA 0x01010000
 #define DDRSS_CTL_269_DATA 0x00000202
@@ -327,14 +328,14 @@
 #define DDRSS_CTL_315_DATA 0x01000101
 #define DDRSS_CTL_316_DATA 0x01010001
 #define DDRSS_CTL_317_DATA 0x00010101
-#define DDRSS_CTL_318_DATA 0x05050503
-#define DDRSS_CTL_319_DATA 0x08080C0C
-#define DDRSS_CTL_320_DATA 0x00090308
-#define DDRSS_CTL_321_DATA 0x000C030F
-#define DDRSS_CTL_322_DATA 0x000C0311
-#define DDRSS_CTL_323_DATA 0x0C090011
+#define DDRSS_CTL_318_DATA 0x05070703
+#define DDRSS_CTL_319_DATA 0x0A081414
+#define DDRSS_CTL_320_DATA 0x0009030A
+#define DDRSS_CTL_321_DATA 0x080C030F
+#define DDRSS_CTL_322_DATA 0x080C0306
+#define DDRSS_CTL_323_DATA 0x0C090006
 #define DDRSS_CTL_324_DATA 0x0100000C
-#define DDRSS_CTL_325_DATA 0x03020301
+#define DDRSS_CTL_325_DATA 0x05020501
 #define DDRSS_CTL_326_DATA 0x00000002
 #define DDRSS_CTL_327_DATA 0x00000000
 #define DDRSS_CTL_328_DATA 0x00010000
@@ -396,7 +397,7 @@
 #define DDRSS_CTL_384_DATA 0x00000000
 #define DDRSS_CTL_385_DATA 0x00000000
 #define DDRSS_CTL_386_DATA 0x00000000
-#define DDRSS_CTL_387_DATA 0x26261B00
+#define DDRSS_CTL_387_DATA 0x2E2E1B00
 #define DDRSS_CTL_388_DATA 0x000A0000
 #define DDRSS_CTL_389_DATA 0x00000176
 #define DDRSS_CTL_390_DATA 0x00000200
@@ -406,22 +407,22 @@
 #define DDRSS_CTL_394_DATA 0x00000462
 #define DDRSS_CTL_395_DATA 0x00000E9C
 #define DDRSS_CTL_396_DATA 0x00000204
-#define DDRSS_CTL_397_DATA 0x00001850
+#define DDRSS_CTL_397_DATA 0x00002890
 #define DDRSS_CTL_398_DATA 0x00000200
 #define DDRSS_CTL_399_DATA 0x00000200
 #define DDRSS_CTL_400_DATA 0x00000200
 #define DDRSS_CTL_401_DATA 0x00000200
-#define DDRSS_CTL_402_DATA 0x000048F0
-#define DDRSS_CTL_403_DATA 0x0000F320
-#define DDRSS_CTL_404_DATA 0x00000408
-#define DDRSS_CTL_405_DATA 0x00001850
+#define DDRSS_CTL_402_DATA 0x000079B0
+#define DDRSS_CTL_403_DATA 0x000195A0
+#define DDRSS_CTL_404_DATA 0x0000080E
+#define DDRSS_CTL_405_DATA 0x00002890
 #define DDRSS_CTL_406_DATA 0x00000200
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
 #define DDRSS_CTL_409_DATA 0x00000200
-#define DDRSS_CTL_410_DATA 0x000048F0
-#define DDRSS_CTL_411_DATA 0x0000F320
-#define DDRSS_CTL_412_DATA 0x02020408
+#define DDRSS_CTL_410_DATA 0x000079B0
+#define DDRSS_CTL_411_DATA 0x000195A0
+#define DDRSS_CTL_412_DATA 0x0202080E
 #define DDRSS_CTL_413_DATA 0x03030202
 #define DDRSS_CTL_414_DATA 0x00000022
 #define DDRSS_CTL_415_DATA 0x00000000
@@ -432,13 +433,13 @@
 #define DDRSS_CTL_420_DATA 0x00000000
 #define DDRSS_CTL_421_DATA 0x00030000
 #define DDRSS_CTL_422_DATA 0x0006001E
-#define DDRSS_CTL_423_DATA 0x000E0026
-#define DDRSS_CTL_424_DATA 0x000E0026
+#define DDRSS_CTL_423_DATA 0x0013002B
+#define DDRSS_CTL_424_DATA 0x0013002B
 #define DDRSS_CTL_425_DATA 0x00000000
 #define DDRSS_CTL_426_DATA 0x00000000
 #define DDRSS_CTL_427_DATA 0x02000000
 #define DDRSS_CTL_428_DATA 0x01000404
-#define DDRSS_CTL_429_DATA 0x01080108
+#define DDRSS_CTL_429_DATA 0x05120512
 #define DDRSS_CTL_430_DATA 0x00000105
 #define DDRSS_CTL_431_DATA 0x00010101
 #define DDRSS_CTL_432_DATA 0x00010101
@@ -447,8 +448,8 @@
 #define DDRSS_CTL_435_DATA 0x02000201
 #define DDRSS_CTL_436_DATA 0x02010000
 #define DDRSS_CTL_437_DATA 0x00000200
-#define DDRSS_CTL_438_DATA 0x10060000
-#define DDRSS_CTL_439_DATA 0x00000110
+#define DDRSS_CTL_438_DATA 0x18060000
+#define DDRSS_CTL_439_DATA 0x00000118
 #define DDRSS_CTL_440_DATA 0xFFFFFFFF
 #define DDRSS_CTL_441_DATA 0xFFFFFFFF
 #define DDRSS_CTL_442_DATA 0x00000000
@@ -504,10 +505,10 @@
 #define DDRSS_PI_32_DATA 0x00000000
 #define DDRSS_PI_33_DATA 0x01010102
 #define DDRSS_PI_34_DATA 0x00000000
-#define DDRSS_PI_35_DATA 0x000000AA
-#define DDRSS_PI_36_DATA 0x00000055
-#define DDRSS_PI_37_DATA 0x000000B5
-#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_35_DATA 0x55555A5A
+#define DDRSS_PI_36_DATA 0x5555A5A5
+#define DDRSS_PI_37_DATA 0x00005A5A
+#define DDRSS_PI_38_DATA 0x0000A5A5
 #define DDRSS_PI_39_DATA 0x00000056
 #define DDRSS_PI_40_DATA 0x000000A9
 #define DDRSS_PI_41_DATA 0x000000A9
@@ -515,12 +516,12 @@
 #define DDRSS_PI_43_DATA 0x00000000
 #define DDRSS_PI_44_DATA 0x00000000
 #define DDRSS_PI_45_DATA 0x000F0F00
-#define DDRSS_PI_46_DATA 0x00000015
+#define DDRSS_PI_46_DATA 0x00000017
 #define DDRSS_PI_47_DATA 0x000007D0
 #define DDRSS_PI_48_DATA 0x00000300
 #define DDRSS_PI_49_DATA 0x00000000
 #define DDRSS_PI_50_DATA 0x00000000
-#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_51_DATA 0x04080000
 #define DDRSS_PI_52_DATA 0x00010101
 #define DDRSS_PI_53_DATA 0x00000000
 #define DDRSS_PI_54_DATA 0x00030000
@@ -632,18 +633,18 @@
 #define DDRSS_PI_160_DATA 0x00000000
 #define DDRSS_PI_161_DATA 0x00010000
 #define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x10100100
+#define DDRSS_PI_163_DATA 0x1B1B0100
 #define DDRSS_PI_164_DATA 0x00000034
-#define DDRSS_PI_165_DATA 0x00000043
-#define DDRSS_PI_166_DATA 0x00020043
+#define DDRSS_PI_165_DATA 0x00000051
+#define DDRSS_PI_166_DATA 0x00020051
 #define DDRSS_PI_167_DATA 0x02000200
-#define DDRSS_PI_168_DATA 0x1C080C04
-#define DDRSS_PI_169_DATA 0x000E1C08
+#define DDRSS_PI_168_DATA 0x300C0C04
+#define DDRSS_PI_169_DATA 0x000E300C
 #define DDRSS_PI_170_DATA 0x000000BB
-#define DDRSS_PI_171_DATA 0x000000E0
-#define DDRSS_PI_172_DATA 0x00000C28
-#define DDRSS_PI_173_DATA 0x000000E0
-#define DDRSS_PI_174_DATA 0x04000C28
+#define DDRSS_PI_171_DATA 0x00000176
+#define DDRSS_PI_172_DATA 0x00001448
+#define DDRSS_PI_173_DATA 0x00000176
+#define DDRSS_PI_174_DATA 0x04001448
 #define DDRSS_PI_175_DATA 0x01010404
 #define DDRSS_PI_176_DATA 0x00001501
 #define DDRSS_PI_177_DATA 0x00150015
@@ -652,82 +653,82 @@
 #define DDRSS_PI_180_DATA 0x00000000
 #define DDRSS_PI_181_DATA 0x01010101
 #define DDRSS_PI_182_DATA 0x00000101
-#define DDRSS_PI_183_DATA 0x00000000
-#define DDRSS_PI_184_DATA 0x00000000
-#define DDRSS_PI_185_DATA 0x08040000
-#define DDRSS_PI_186_DATA 0x04040208
+#define DDRSS_PI_183_DATA 0x00000100
+#define DDRSS_PI_184_DATA 0x00000100
+#define DDRSS_PI_185_DATA 0x0E040100
+#define DDRSS_PI_186_DATA 0x0808020E
 #define DDRSS_PI_187_DATA 0x00040402
 #define DDRSS_PI_188_DATA 0x000C8034
-#define DDRSS_PI_189_DATA 0x0014003C
-#define DDRSS_PI_190_DATA 0x0014003C
+#define DDRSS_PI_189_DATA 0x00198041
+#define DDRSS_PI_190_DATA 0x00198041
 #define DDRSS_PI_191_DATA 0x01010101
 #define DDRSS_PI_192_DATA 0x0002000D
-#define DDRSS_PI_193_DATA 0x000200C8
-#define DDRSS_PI_194_DATA 0x010000C8
+#define DDRSS_PI_193_DATA 0x0002014E
+#define DDRSS_PI_194_DATA 0x0100014E
 #define DDRSS_PI_195_DATA 0x000E000E
-#define DDRSS_PI_196_DATA 0x00C90100
-#define DDRSS_PI_197_DATA 0x010000C9
-#define DDRSS_PI_198_DATA 0x00C900C9
+#define DDRSS_PI_196_DATA 0x014F0100
+#define DDRSS_PI_197_DATA 0x0100014F
+#define DDRSS_PI_198_DATA 0x014F014F
 #define DDRSS_PI_199_DATA 0x32103200
 #define DDRSS_PI_200_DATA 0x01013210
 #define DDRSS_PI_201_DATA 0x0A070601
-#define DDRSS_PI_202_DATA 0x0D09070D
-#define DDRSS_PI_203_DATA 0x0D09070D
-#define DDRSS_PI_204_DATA 0x0000C00D
+#define DDRSS_PI_202_DATA 0x140D080D
+#define DDRSS_PI_203_DATA 0x140D0810
+#define DDRSS_PI_204_DATA 0x0000C010
 #define DDRSS_PI_205_DATA 0x00C01000
 #define DDRSS_PI_206_DATA 0x00C01000
 #define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x0016000D
-#define DDRSS_PI_209_DATA 0x001600C8
-#define DDRSS_PI_210_DATA 0x001100C8
+#define DDRSS_PI_208_DATA 0x001C000D
+#define DDRSS_PI_209_DATA 0x001C014E
+#define DDRSS_PI_210_DATA 0x0011014E
 #define DDRSS_PI_211_DATA 0x32000056
 #define DDRSS_PI_212_DATA 0x00000301
-#define DDRSS_PI_213_DATA 0x00580020
+#define DDRSS_PI_213_DATA 0x005A002A
 #define DDRSS_PI_214_DATA 0x03013212
-#define DDRSS_PI_215_DATA 0x00002000
-#define DDRSS_PI_216_DATA 0x32120058
+#define DDRSS_PI_215_DATA 0x00002A00
+#define DDRSS_PI_216_DATA 0x3212005A
 #define DDRSS_PI_217_DATA 0x09000301
 #define DDRSS_PI_218_DATA 0x04010504
 #define DDRSS_PI_219_DATA 0x0400062B
 #define DDRSS_PI_220_DATA 0x0A032001
-#define DDRSS_PI_221_DATA 0x1113090A
-#define DDRSS_PI_222_DATA 0x0000120C
-#define DDRSS_PI_223_DATA 0x240062B8
-#define DDRSS_PI_224_DATA 0x0C0C2003
-#define DDRSS_PI_225_DATA 0x1113090A
-#define DDRSS_PI_226_DATA 0x0000120C
-#define DDRSS_PI_227_DATA 0x240062B8
-#define DDRSS_PI_228_DATA 0x0C0C2003
-#define DDRSS_PI_229_DATA 0x0001760A
+#define DDRSS_PI_221_DATA 0x1C1F0B0A
+#define DDRSS_PI_222_DATA 0x00001D12
+#define DDRSS_PI_223_DATA 0x3C00A488
+#define DDRSS_PI_224_DATA 0x13142005
+#define DDRSS_PI_225_DATA 0x1C1F0B0E
+#define DDRSS_PI_226_DATA 0x00001D12
+#define DDRSS_PI_227_DATA 0x3C00A488
+#define DDRSS_PI_228_DATA 0x13142005
+#define DDRSS_PI_229_DATA 0x0001760E
 #define DDRSS_PI_230_DATA 0x00000E9C
-#define DDRSS_PI_231_DATA 0x00001850
-#define DDRSS_PI_232_DATA 0x0000F320
-#define DDRSS_PI_233_DATA 0x00001850
-#define DDRSS_PI_234_DATA 0x0000F320
-#define DDRSS_PI_235_DATA 0x00E6000F
-#define DDRSS_PI_236_DATA 0x030300E6
+#define DDRSS_PI_231_DATA 0x00002890
+#define DDRSS_PI_232_DATA 0x000195A0
+#define DDRSS_PI_233_DATA 0x00002890
+#define DDRSS_PI_234_DATA 0x000195A0
+#define DDRSS_PI_235_DATA 0x0180000F
+#define DDRSS_PI_236_DATA 0x03030180
 #define DDRSS_PI_237_DATA 0x00271003
 #define DDRSS_PI_238_DATA 0x000186A0
 #define DDRSS_PI_239_DATA 0x00000005
 #define DDRSS_PI_240_DATA 0x00000064
 #define DDRSS_PI_241_DATA 0x0000000F
-#define DDRSS_PI_242_DATA 0x00027100
+#define DDRSS_PI_242_DATA 0x000411AB
 #define DDRSS_PI_243_DATA 0x000186A0
 #define DDRSS_PI_244_DATA 0x00000005
-#define DDRSS_PI_245_DATA 0x00000640
-#define DDRSS_PI_246_DATA 0x000000E6
-#define DDRSS_PI_247_DATA 0x00027100
+#define DDRSS_PI_245_DATA 0x00000A6B
+#define DDRSS_PI_246_DATA 0x00000180
+#define DDRSS_PI_247_DATA 0x000411AB
 #define DDRSS_PI_248_DATA 0x000186A0
 #define DDRSS_PI_249_DATA 0x00000005
-#define DDRSS_PI_250_DATA 0x00000640
-#define DDRSS_PI_251_DATA 0x010000E6
+#define DDRSS_PI_250_DATA 0x00000A6B
+#define DDRSS_PI_251_DATA 0x01000180
 #define DDRSS_PI_252_DATA 0x00320040
 #define DDRSS_PI_253_DATA 0x00010008
-#define DDRSS_PI_254_DATA 0x03200040
-#define DDRSS_PI_255_DATA 0x00010018
-#define DDRSS_PI_256_DATA 0x03200040
-#define DDRSS_PI_257_DATA 0x00000318
-#define DDRSS_PI_258_DATA 0x00280028
+#define DDRSS_PI_254_DATA 0x05360040
+#define DDRSS_PI_255_DATA 0x00010028
+#define DDRSS_PI_256_DATA 0x05360040
+#define DDRSS_PI_257_DATA 0x00000328
+#define DDRSS_PI_258_DATA 0x00430043
 #define DDRSS_PI_259_DATA 0x00040404
 #define DDRSS_PI_260_DATA 0x00000055
 #define DDRSS_PI_261_DATA 0x55003C5A
@@ -746,27 +747,27 @@
 #define DDRSS_PI_274_DATA 0x00000000
 #define DDRSS_PI_275_DATA 0x002B0084
 #define DDRSS_PI_276_DATA 0x00150000
-#define DDRSS_PI_277_DATA 0x362B12A4
+#define DDRSS_PI_277_DATA 0x362B24C4
 #define DDRSS_PI_278_DATA 0x00150F27
-#define DDRSS_PI_279_DATA 0x362B12A4
+#define DDRSS_PI_279_DATA 0x362B24C4
 #define DDRSS_PI_280_DATA 0x00150F27
 #define DDRSS_PI_281_DATA 0x002B0084
 #define DDRSS_PI_282_DATA 0x00150000
-#define DDRSS_PI_283_DATA 0x362B12A4
+#define DDRSS_PI_283_DATA 0x362B24C4
 #define DDRSS_PI_284_DATA 0x00150F27
-#define DDRSS_PI_285_DATA 0x362B12A4
+#define DDRSS_PI_285_DATA 0x362B24C4
 #define DDRSS_PI_286_DATA 0x00150F27
 #define DDRSS_PI_287_DATA 0x002B0084
 #define DDRSS_PI_288_DATA 0x00150000
-#define DDRSS_PI_289_DATA 0x362B12A4
+#define DDRSS_PI_289_DATA 0x362B24C4
 #define DDRSS_PI_290_DATA 0x00150F27
-#define DDRSS_PI_291_DATA 0x362B12A4
+#define DDRSS_PI_291_DATA 0x362B24C4
 #define DDRSS_PI_292_DATA 0x00150F27
 #define DDRSS_PI_293_DATA 0x002B0084
 #define DDRSS_PI_294_DATA 0x00150000
-#define DDRSS_PI_295_DATA 0x362B12A4
+#define DDRSS_PI_295_DATA 0x362B24C4
 #define DDRSS_PI_296_DATA 0x00150F27
-#define DDRSS_PI_297_DATA 0x362B12A4
+#define DDRSS_PI_297_DATA 0x362B24C4
 #define DDRSS_PI_298_DATA 0x00150F27
 #define DDRSS_PI_299_DATA 0x00000000
 
@@ -788,10 +789,10 @@
 #define DDRSS_PHY_15_DATA 0x00030066
 #define DDRSS_PHY_16_DATA 0x00000000
 #define DDRSS_PHY_17_DATA 0x00000301
-#define DDRSS_PHY_18_DATA 0x0000AAAA
-#define DDRSS_PHY_19_DATA 0x00005555
-#define DDRSS_PHY_20_DATA 0x0000B5B5
-#define DDRSS_PHY_21_DATA 0x00004A4A
+#define DDRSS_PHY_18_DATA 0x55555A5A
+#define DDRSS_PHY_19_DATA 0x5555A5A5
+#define DDRSS_PHY_20_DATA 0x00005A5A
+#define DDRSS_PHY_21_DATA 0x0000A5A5
 #define DDRSS_PHY_22_DATA 0x00005656
 #define DDRSS_PHY_23_DATA 0x0000A9A9
 #define DDRSS_PHY_24_DATA 0x0000A9A9
@@ -862,7 +863,7 @@
 #define DDRSS_PHY_89_DATA 0x10100303
 #define DDRSS_PHY_90_DATA 0x10101010
 #define DDRSS_PHY_91_DATA 0x10101010
-#define DDRSS_PHY_92_DATA 0x00011010
+#define DDRSS_PHY_92_DATA 0x00021010
 #define DDRSS_PHY_93_DATA 0x00100010
 #define DDRSS_PHY_94_DATA 0x00100010
 #define DDRSS_PHY_95_DATA 0x00100010
@@ -872,18 +873,18 @@
 #define DDRSS_PHY_99_DATA 0x31C06000
 #define DDRSS_PHY_100_DATA 0x07AB0340
 #define DDRSS_PHY_101_DATA 0x00C0C001
-#define DDRSS_PHY_102_DATA 0x05040001
+#define DDRSS_PHY_102_DATA 0x09080001
 #define DDRSS_PHY_103_DATA 0x10001000
-#define DDRSS_PHY_104_DATA 0x0C053E42
-#define DDRSS_PHY_105_DATA 0x0F0C1D01
+#define DDRSS_PHY_104_DATA 0x0C063E42
+#define DDRSS_PHY_105_DATA 0x0F0C2701
 #define DDRSS_PHY_106_DATA 0x01000140
-#define DDRSS_PHY_107_DATA 0x0C000420
-#define DDRSS_PHY_108_DATA 0x000001CC
+#define DDRSS_PHY_107_DATA 0x04000420
+#define DDRSS_PHY_108_DATA 0x00000255
 #define DDRSS_PHY_109_DATA 0x0A0000D0
 #define DDRSS_PHY_110_DATA 0x00030200
 #define DDRSS_PHY_111_DATA 0x02800000
 #define DDRSS_PHY_112_DATA 0x80800000
-#define DDRSS_PHY_113_DATA 0x00052010
+#define DDRSS_PHY_113_DATA 0x00092010
 #define DDRSS_PHY_114_DATA 0x76543210
 #define DDRSS_PHY_115_DATA 0x00000008
 #define DDRSS_PHY_116_DATA 0x02800280
@@ -900,8 +901,8 @@
 #define DDRSS_PHY_127_DATA 0x00A000A0
 #define DDRSS_PHY_128_DATA 0x00A000A0
 #define DDRSS_PHY_129_DATA 0x00A000A0
-#define DDRSS_PHY_130_DATA 0x011900A0
-#define DDRSS_PHY_131_DATA 0x01A00002
+#define DDRSS_PHY_130_DATA 0x01C400A0
+#define DDRSS_PHY_131_DATA 0x01A00003
 #define DDRSS_PHY_132_DATA 0x00000000
 #define DDRSS_PHY_133_DATA 0x00000000
 #define DDRSS_PHY_134_DATA 0x00080200
@@ -1044,10 +1045,10 @@
 #define DDRSS_PHY_271_DATA 0x00030066
 #define DDRSS_PHY_272_DATA 0x00000000
 #define DDRSS_PHY_273_DATA 0x00000301
-#define DDRSS_PHY_274_DATA 0x0000AAAA
-#define DDRSS_PHY_275_DATA 0x00005555
-#define DDRSS_PHY_276_DATA 0x0000B5B5
-#define DDRSS_PHY_277_DATA 0x00004A4A
+#define DDRSS_PHY_274_DATA 0x55555A5A
+#define DDRSS_PHY_275_DATA 0x5555A5A5
+#define DDRSS_PHY_276_DATA 0x00005A5A
+#define DDRSS_PHY_277_DATA 0x0000A5A5
 #define DDRSS_PHY_278_DATA 0x00005656
 #define DDRSS_PHY_279_DATA 0x0000A9A9
 #define DDRSS_PHY_280_DATA 0x0000A9A9
@@ -1118,7 +1119,7 @@
 #define DDRSS_PHY_345_DATA 0x10100303
 #define DDRSS_PHY_346_DATA 0x10101010
 #define DDRSS_PHY_347_DATA 0x10101010
-#define DDRSS_PHY_348_DATA 0x00011010
+#define DDRSS_PHY_348_DATA 0x00021010
 #define DDRSS_PHY_349_DATA 0x00100010
 #define DDRSS_PHY_350_DATA 0x00100010
 #define DDRSS_PHY_351_DATA 0x00100010
@@ -1128,18 +1129,18 @@
 #define DDRSS_PHY_355_DATA 0x31C06000
 #define DDRSS_PHY_356_DATA 0x07AB0340
 #define DDRSS_PHY_357_DATA 0x00C0C001
-#define DDRSS_PHY_358_DATA 0x05040001
+#define DDRSS_PHY_358_DATA 0x09080001
 #define DDRSS_PHY_359_DATA 0x10001000
-#define DDRSS_PHY_360_DATA 0x0C053E42
-#define DDRSS_PHY_361_DATA 0x0F0C1D01
+#define DDRSS_PHY_360_DATA 0x0C063E42
+#define DDRSS_PHY_361_DATA 0x0F0C2701
 #define DDRSS_PHY_362_DATA 0x01000140
-#define DDRSS_PHY_363_DATA 0x0C000420
-#define DDRSS_PHY_364_DATA 0x000001CC
+#define DDRSS_PHY_363_DATA 0x04000420
+#define DDRSS_PHY_364_DATA 0x00000255
 #define DDRSS_PHY_365_DATA 0x0A0000D0
 #define DDRSS_PHY_366_DATA 0x00030200
 #define DDRSS_PHY_367_DATA 0x02800000
 #define DDRSS_PHY_368_DATA 0x80800000
-#define DDRSS_PHY_369_DATA 0x00052010
+#define DDRSS_PHY_369_DATA 0x00092010
 #define DDRSS_PHY_370_DATA 0x76543210
 #define DDRSS_PHY_371_DATA 0x00000008
 #define DDRSS_PHY_372_DATA 0x02800280
@@ -1156,8 +1157,8 @@
 #define DDRSS_PHY_383_DATA 0x00A000A0
 #define DDRSS_PHY_384_DATA 0x00A000A0
 #define DDRSS_PHY_385_DATA 0x00A000A0
-#define DDRSS_PHY_386_DATA 0x011900A0
-#define DDRSS_PHY_387_DATA 0x01A00002
+#define DDRSS_PHY_386_DATA 0x01C400A0
+#define DDRSS_PHY_387_DATA 0x01A00003
 #define DDRSS_PHY_388_DATA 0x00000000
 #define DDRSS_PHY_389_DATA 0x00000000
 #define DDRSS_PHY_390_DATA 0x00080200
@@ -1300,10 +1301,10 @@
 #define DDRSS_PHY_527_DATA 0x00030066
 #define DDRSS_PHY_528_DATA 0x00000000
 #define DDRSS_PHY_529_DATA 0x00000301
-#define DDRSS_PHY_530_DATA 0x0000AAAA
-#define DDRSS_PHY_531_DATA 0x00005555
-#define DDRSS_PHY_532_DATA 0x0000B5B5
-#define DDRSS_PHY_533_DATA 0x00004A4A
+#define DDRSS_PHY_530_DATA 0x55555A5A
+#define DDRSS_PHY_531_DATA 0x5555A5A5
+#define DDRSS_PHY_532_DATA 0x00005A5A
+#define DDRSS_PHY_533_DATA 0x0000A5A5
 #define DDRSS_PHY_534_DATA 0x00005656
 #define DDRSS_PHY_535_DATA 0x0000A9A9
 #define DDRSS_PHY_536_DATA 0x0000A9A9
@@ -1374,7 +1375,7 @@
 #define DDRSS_PHY_601_DATA 0x10100303
 #define DDRSS_PHY_602_DATA 0x10101010
 #define DDRSS_PHY_603_DATA 0x10101010
-#define DDRSS_PHY_604_DATA 0x00011010
+#define DDRSS_PHY_604_DATA 0x00021010
 #define DDRSS_PHY_605_DATA 0x00100010
 #define DDRSS_PHY_606_DATA 0x00100010
 #define DDRSS_PHY_607_DATA 0x00100010
@@ -1384,18 +1385,18 @@
 #define DDRSS_PHY_611_DATA 0x31C06000
 #define DDRSS_PHY_612_DATA 0x07AB0340
 #define DDRSS_PHY_613_DATA 0x00C0C001
-#define DDRSS_PHY_614_DATA 0x05040001
+#define DDRSS_PHY_614_DATA 0x09080001
 #define DDRSS_PHY_615_DATA 0x10001000
-#define DDRSS_PHY_616_DATA 0x0C053E42
-#define DDRSS_PHY_617_DATA 0x0F0C1D01
+#define DDRSS_PHY_616_DATA 0x0C063E42
+#define DDRSS_PHY_617_DATA 0x0F0C2701
 #define DDRSS_PHY_618_DATA 0x01000140
-#define DDRSS_PHY_619_DATA 0x0C000420
-#define DDRSS_PHY_620_DATA 0x000001CC
+#define DDRSS_PHY_619_DATA 0x04000420
+#define DDRSS_PHY_620_DATA 0x00000255
 #define DDRSS_PHY_621_DATA 0x0A0000D0
 #define DDRSS_PHY_622_DATA 0x00030200
 #define DDRSS_PHY_623_DATA 0x02800000
 #define DDRSS_PHY_624_DATA 0x80800000
-#define DDRSS_PHY_625_DATA 0x00052010
+#define DDRSS_PHY_625_DATA 0x00092010
 #define DDRSS_PHY_626_DATA 0x76543210
 #define DDRSS_PHY_627_DATA 0x00000008
 #define DDRSS_PHY_628_DATA 0x02800280
@@ -1412,8 +1413,8 @@
 #define DDRSS_PHY_639_DATA 0x00A000A0
 #define DDRSS_PHY_640_DATA 0x00A000A0
 #define DDRSS_PHY_641_DATA 0x00A000A0
-#define DDRSS_PHY_642_DATA 0x011900A0
-#define DDRSS_PHY_643_DATA 0x01A00002
+#define DDRSS_PHY_642_DATA 0x01C400A0
+#define DDRSS_PHY_643_DATA 0x01A00003
 #define DDRSS_PHY_644_DATA 0x00000000
 #define DDRSS_PHY_645_DATA 0x00000000
 #define DDRSS_PHY_646_DATA 0x00080200
@@ -1556,10 +1557,10 @@
 #define DDRSS_PHY_783_DATA 0x00030066
 #define DDRSS_PHY_784_DATA 0x00000000
 #define DDRSS_PHY_785_DATA 0x00000301
-#define DDRSS_PHY_786_DATA 0x0000AAAA
-#define DDRSS_PHY_787_DATA 0x00005555
-#define DDRSS_PHY_788_DATA 0x0000B5B5
-#define DDRSS_PHY_789_DATA 0x00004A4A
+#define DDRSS_PHY_786_DATA 0x55555A5A
+#define DDRSS_PHY_787_DATA 0x5555A5A5
+#define DDRSS_PHY_788_DATA 0x00005A5A
+#define DDRSS_PHY_789_DATA 0x0000A5A5
 #define DDRSS_PHY_790_DATA 0x00005656
 #define DDRSS_PHY_791_DATA 0x0000A9A9
 #define DDRSS_PHY_792_DATA 0x0000A9A9
@@ -1630,7 +1631,7 @@
 #define DDRSS_PHY_857_DATA 0x10100303
 #define DDRSS_PHY_858_DATA 0x10101010
 #define DDRSS_PHY_859_DATA 0x10101010
-#define DDRSS_PHY_860_DATA 0x00011010
+#define DDRSS_PHY_860_DATA 0x00021010
 #define DDRSS_PHY_861_DATA 0x00100010
 #define DDRSS_PHY_862_DATA 0x00100010
 #define DDRSS_PHY_863_DATA 0x00100010
@@ -1640,18 +1641,18 @@
 #define DDRSS_PHY_867_DATA 0x31C06000
 #define DDRSS_PHY_868_DATA 0x07AB0340
 #define DDRSS_PHY_869_DATA 0x00C0C001
-#define DDRSS_PHY_870_DATA 0x05040001
+#define DDRSS_PHY_870_DATA 0x09080001
 #define DDRSS_PHY_871_DATA 0x10001000
-#define DDRSS_PHY_872_DATA 0x0C053E42
-#define DDRSS_PHY_873_DATA 0x0F0C1D01
+#define DDRSS_PHY_872_DATA 0x0C063E42
+#define DDRSS_PHY_873_DATA 0x0F0C2701
 #define DDRSS_PHY_874_DATA 0x01000140
-#define DDRSS_PHY_875_DATA 0x0C000420
-#define DDRSS_PHY_876_DATA 0x000001CC
+#define DDRSS_PHY_875_DATA 0x04000420
+#define DDRSS_PHY_876_DATA 0x00000255
 #define DDRSS_PHY_877_DATA 0x0A0000D0
 #define DDRSS_PHY_878_DATA 0x00030200
 #define DDRSS_PHY_879_DATA 0x02800000
 #define DDRSS_PHY_880_DATA 0x80800000
-#define DDRSS_PHY_881_DATA 0x00052010
+#define DDRSS_PHY_881_DATA 0x00092010
 #define DDRSS_PHY_882_DATA 0x76543210
 #define DDRSS_PHY_883_DATA 0x00000008
 #define DDRSS_PHY_884_DATA 0x02800280
@@ -1668,13 +1669,13 @@
 #define DDRSS_PHY_895_DATA 0x00A000A0
 #define DDRSS_PHY_896_DATA 0x00A000A0
 #define DDRSS_PHY_897_DATA 0x00A000A0
-#define DDRSS_PHY_898_DATA 0x011900A0
-#define DDRSS_PHY_899_DATA 0x01A00002
+#define DDRSS_PHY_898_DATA 0x01C400A0
+#define DDRSS_PHY_899_DATA 0x01A00003
 #define DDRSS_PHY_900_DATA 0x00000000
 #define DDRSS_PHY_901_DATA 0x00000000
 #define DDRSS_PHY_902_DATA 0x00080200
 #define DDRSS_PHY_903_DATA 0x00000000
-#define DDRSS_PHY_904_DATA 0x20202010
+#define DDRSS_PHY_904_DATA 0x20202000
 #define DDRSS_PHY_905_DATA 0x20202020
 #define DDRSS_PHY_906_DATA 0xF0F02020
 #define DDRSS_PHY_907_DATA 0x00000000
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 0491432060..69d8600c19 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -6,7 +6,7 @@
 /dts-v1/;
 
 #include "k3-j7200-som-p0.dtsi"
-#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
+#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
 #include "k3-j721e-ddr.dtsi"
 
 / {
-- 
2.17.1