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From: Linus Walleij <linus.walleij@linaro.org>
To: arm@kernel.org, soc@kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
	Linus Walleij <linus.walleij@linaro.org>,
	Corentin Labbe <clabbe@baylibre.com>
Subject: [PATCH] ARM: dts: ixp4xx: Add crypto engine
Date: Sat,  5 Jun 2021 18:10:07 +0200	[thread overview]
Message-ID: <20210605161007.3397216-1-linus.walleij@linaro.org> (raw)

Add the crypto engine as a child of the NPE.

Cc: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ARM SoC folks: please queue this patch on top of the
other ixp4xx changes sent by pull request.
---
 arch/arm/boot/dts/intel-ixp4xx.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
index 528d5dc09cfc..a50427ad05e7 100644
--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
@@ -113,6 +113,14 @@ timer@c8005000 {
 		npe: npe@c8006000 {
 			compatible = "intel,ixp4xx-network-processing-engine";
 			reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+
+			/* NPE-C contains a crypto accelerator */
+			crypto {
+				compatible = "intel,ixp4xx-crypto";
+				intel,npe-handle = <&npe 2>;
+				queue-rx = <&qmgr 30>;
+				queue-txready = <&qmgr 29>;
+			};
 		};
 
 		/* This is known as EthB */
-- 
2.31.1


WARNING: multiple messages have this Message-ID (diff)
From: Linus Walleij <linus.walleij@linaro.org>
To: arm@kernel.org, soc@kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
	Linus Walleij <linus.walleij@linaro.org>,
	Corentin Labbe <clabbe@baylibre.com>
Subject: [PATCH] ARM: dts: ixp4xx: Add crypto engine
Date: Sat,  5 Jun 2021 18:10:07 +0200	[thread overview]
Message-ID: <20210605161007.3397216-1-linus.walleij@linaro.org> (raw)
Message-ID: <20210605161007.rnqOzi_AUH4sagW5AvflMv9XD2n5SQC-LePB0ZpHaTQ@z> (raw)

Add the crypto engine as a child of the NPE.

Cc: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ARM SoC folks: please queue this patch on top of the
other ixp4xx changes sent by pull request.
---
 arch/arm/boot/dts/intel-ixp4xx.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
index 528d5dc09cfc..a50427ad05e7 100644
--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
@@ -113,6 +113,14 @@ timer@c8005000 {
 		npe: npe@c8006000 {
 			compatible = "intel,ixp4xx-network-processing-engine";
 			reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+
+			/* NPE-C contains a crypto accelerator */
+			crypto {
+				compatible = "intel,ixp4xx-crypto";
+				intel,npe-handle = <&npe 2>;
+				queue-rx = <&qmgr 30>;
+				queue-txready = <&qmgr 29>;
+			};
 		};
 
 		/* This is known as EthB */
-- 
2.31.1


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             reply	other threads:[~2021-06-05 16:12 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-05 16:10 Linus Walleij [this message]
2021-06-05 16:10 ` [PATCH] ARM: dts: ixp4xx: Add crypto engine Linus Walleij
2021-06-12 16:10 ` patchwork-bot+linux-soc

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