From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: matthew.auld@intel.com, Chris Wilson <chris@chris-wilson.co.uk> Subject: [PATCH 6/9] drm/i915/gt: Export the pinned context constructor Date: Tue, 8 Jun 2021 11:28:43 +0200 [thread overview] Message-ID: <20210608092846.64198-7-thomas.hellstrom@linux.intel.com> (raw) In-Reply-To: <20210608092846.64198-1-thomas.hellstrom@linux.intel.com> From: Chris Wilson <chris@chris-wilson.co.uk> Allow internal clients to create a pinned context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine.h | 9 +++++++++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 21 ++++++++++++++------- 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 8d9184920c51..0862c42b4cac 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -19,7 +19,9 @@ #include "intel_workarounds.h" struct drm_printer; +struct intel_context; struct intel_gt; +struct lock_class_key; /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, * but keeps the logic simple. Indeed, the whole purpose of this macro is just @@ -256,6 +258,13 @@ struct i915_request * intel_engine_find_active_request(struct intel_engine_cs *engine); u32 intel_engine_context_size(struct intel_gt *gt, u8 class); +struct intel_context * +intel_engine_create_pinned_context(struct intel_engine_cs *engine, + struct i915_address_space *vm, + unsigned int ring_size, + unsigned int hwsp, + struct lock_class_key *key, + const char *name); void intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 9ceddfbb1687..ac32fd29d7ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -810,11 +810,13 @@ intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass) #endif } -static struct intel_context * -create_pinned_context(struct intel_engine_cs *engine, - unsigned int hwsp, - struct lock_class_key *key, - const char *name) +struct intel_context * +intel_engine_create_pinned_context(struct intel_engine_cs *engine, + struct i915_address_space *vm, + unsigned int ring_size, + unsigned int hwsp, + struct lock_class_key *key, + const char *name) { struct intel_context *ce; int err; @@ -825,6 +827,10 @@ create_pinned_context(struct intel_engine_cs *engine, __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); ce->timeline = page_pack_bits(NULL, hwsp); + ce->ring = __intel_context_ring_size(ring_size); + + i915_vm_put(ce->vm); + ce->vm = i915_vm_get(vm); err = intel_context_pin(ce); /* perma-pin so it is always available */ if (err) { @@ -863,8 +869,9 @@ create_kernel_context(struct intel_engine_cs *engine) { static struct lock_class_key kernel; - return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR, - &kernel, "kernel_context"); + return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, + I915_GEM_HWS_SEQNO_ADDR, + &kernel, "kernel_context"); } /** -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: matthew.auld@intel.com, Chris Wilson <chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 6/9] drm/i915/gt: Export the pinned context constructor Date: Tue, 8 Jun 2021 11:28:43 +0200 [thread overview] Message-ID: <20210608092846.64198-7-thomas.hellstrom@linux.intel.com> (raw) In-Reply-To: <20210608092846.64198-1-thomas.hellstrom@linux.intel.com> From: Chris Wilson <chris@chris-wilson.co.uk> Allow internal clients to create a pinned context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine.h | 9 +++++++++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 21 ++++++++++++++------- 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 8d9184920c51..0862c42b4cac 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -19,7 +19,9 @@ #include "intel_workarounds.h" struct drm_printer; +struct intel_context; struct intel_gt; +struct lock_class_key; /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, * but keeps the logic simple. Indeed, the whole purpose of this macro is just @@ -256,6 +258,13 @@ struct i915_request * intel_engine_find_active_request(struct intel_engine_cs *engine); u32 intel_engine_context_size(struct intel_gt *gt, u8 class); +struct intel_context * +intel_engine_create_pinned_context(struct intel_engine_cs *engine, + struct i915_address_space *vm, + unsigned int ring_size, + unsigned int hwsp, + struct lock_class_key *key, + const char *name); void intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 9ceddfbb1687..ac32fd29d7ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -810,11 +810,13 @@ intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass) #endif } -static struct intel_context * -create_pinned_context(struct intel_engine_cs *engine, - unsigned int hwsp, - struct lock_class_key *key, - const char *name) +struct intel_context * +intel_engine_create_pinned_context(struct intel_engine_cs *engine, + struct i915_address_space *vm, + unsigned int ring_size, + unsigned int hwsp, + struct lock_class_key *key, + const char *name) { struct intel_context *ce; int err; @@ -825,6 +827,10 @@ create_pinned_context(struct intel_engine_cs *engine, __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); ce->timeline = page_pack_bits(NULL, hwsp); + ce->ring = __intel_context_ring_size(ring_size); + + i915_vm_put(ce->vm); + ce->vm = i915_vm_get(vm); err = intel_context_pin(ce); /* perma-pin so it is always available */ if (err) { @@ -863,8 +869,9 @@ create_kernel_context(struct intel_engine_cs *engine) { static struct lock_class_key kernel; - return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR, - &kernel, "kernel_context"); + return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, + I915_GEM_HWS_SEQNO_ADDR, + &kernel, "kernel_context"); } /** -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-08 9:29 UTC|newest] Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-08 9:28 [PATCH 0/9] Prereqs for TTM accelerated migration Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` [PATCH 1/9] drm/i915: Reference objects on the ww object list Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 17:05 ` Matthew Auld 2021-06-08 17:05 ` [Intel-gfx] " Matthew Auld 2021-06-08 9:28 ` [PATCH 2/9] drm/i915: Break out dma_resv ww locking utilities to separate files Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 17:10 ` Matthew Auld 2021-06-08 17:10 ` [Intel-gfx] " Matthew Auld 2021-06-08 9:28 ` [PATCH 3/9] drm/i915: Introduce a ww transaction helper Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 17:17 ` Matthew Auld 2021-06-08 17:17 ` Matthew Auld 2021-06-08 19:00 ` Thomas Hellström 2021-06-08 19:00 ` Thomas Hellström 2021-06-08 9:28 ` [PATCH 4/9] drm/i915/gt: Add an insert_entry for gen8_ppgtt Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` [PATCH 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` Thomas Hellström [this message] 2021-06-08 9:28 ` [Intel-gfx] [PATCH 6/9] drm/i915/gt: Export the pinned context constructor Thomas Hellström 2021-06-08 9:28 ` [PATCH 7/9] drm/i915/gt: Pipelined page migration Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 16:18 ` Matthew Auld 2021-06-08 16:18 ` Matthew Auld 2021-06-08 19:05 ` Thomas Hellström 2021-06-08 19:05 ` Thomas Hellström 2021-06-08 19:09 ` Thomas Hellström 2021-06-08 19:09 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` [PATCH 8/9] drm/i915/gt: Pipelined clear Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` [PATCH 9/9] drm/i915/gt: Setup a default migration context on the GT Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 12:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prereqs for TTM accelerated migration Patchwork 2021-06-08 12:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2021-06-08 12:32 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
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