From: Jonathan Marek <jonathan@marek.ca> To: freedreno@lists.freedesktop.org Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Jordan Crouse <jordan@cosmicpenguin.net>, Akhil P Oommen <akhilpo@codeaurora.org>, Eric Anholt <eric@anholt.net>, Sharat Masetty <smasetty@codeaurora.org>, linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 3/5] drm/msm/a6xx: add GMU_CX_GMU_CX_FALNEXT_INTF write for a650 Date: Tue, 8 Jun 2021 13:27:46 -0400 [thread overview] Message-ID: <20210608172808.11803-4-jonathan@marek.ca> (raw) In-Reply-To: <20210608172808.11803-1-jonathan@marek.ca> downstream msm-5.14 kernel added a write to this register, so match that. Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +++- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index c1ee02d6371d..0f3390eab55e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -751,8 +751,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) int ret; u32 chipid; - if (adreno_is_a650(adreno_gpu)) + if (adreno_is_a650(adreno_gpu)) { + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); + } if (state == GMU_WARM_BOOT) { ret = a6xx_rpmh_start(gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 5a43d3090b0c..eeef3d6d89b8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -292,6 +292,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0 +#define REF_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1 + #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101 -- 2.26.1
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Marek <jonathan@marek.ca> To: freedreno@lists.freedesktop.org Cc: David Airlie <airlied@linux.ie>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <linux-arm-msm@vger.kernel.org>, Sharat Masetty <smasetty@codeaurora.org>, Akhil P Oommen <akhilpo@codeaurora.org>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <dri-devel@lists.freedesktop.org>, Jordan Crouse <jordan@cosmicpenguin.net>, Sean Paul <sean@poorly.run>, open list <linux-kernel@vger.kernel.org> Subject: [PATCH v3 3/5] drm/msm/a6xx: add GMU_CX_GMU_CX_FALNEXT_INTF write for a650 Date: Tue, 8 Jun 2021 13:27:46 -0400 [thread overview] Message-ID: <20210608172808.11803-4-jonathan@marek.ca> (raw) In-Reply-To: <20210608172808.11803-1-jonathan@marek.ca> downstream msm-5.14 kernel added a write to this register, so match that. Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +++- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index c1ee02d6371d..0f3390eab55e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -751,8 +751,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) int ret; u32 chipid; - if (adreno_is_a650(adreno_gpu)) + if (adreno_is_a650(adreno_gpu)) { + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); + } if (state == GMU_WARM_BOOT) { ret = a6xx_rpmh_start(gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 5a43d3090b0c..eeef3d6d89b8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -292,6 +292,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0 +#define REF_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1 + #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101 -- 2.26.1
next prev parent reply other threads:[~2021-06-08 17:30 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-08 17:27 [PATCH v3 0/5] drm/msm/a6xx: add support for Adreno 660 GPU Jonathan Marek 2021-06-08 17:27 ` Jonathan Marek 2021-06-08 17:27 ` [PATCH v3 1/5] drm/msm: remove unused icc_path/ocmem_icc_path Jonathan Marek 2021-06-08 17:27 ` Jonathan Marek 2021-06-08 17:27 ` [PATCH v3 2/5] drm/msm/a6xx: use AOP-initialized PDC for a650 Jonathan Marek 2021-06-08 17:27 ` Jonathan Marek 2021-06-08 17:27 ` Jonathan Marek [this message] 2021-06-08 17:27 ` [PATCH v3 3/5] drm/msm/a6xx: add GMU_CX_GMU_CX_FALNEXT_INTF write " Jonathan Marek 2021-06-08 18:03 ` Jonathan Marek 2021-06-08 18:03 ` Jonathan Marek 2021-06-08 17:27 ` [PATCH v3 4/5] drm/msm/a6xx: add missing PC_DBG_ECO_CNTL bit for a640/a650 Jonathan Marek 2021-06-08 17:27 ` Jonathan Marek 2021-06-08 17:27 ` [PATCH v3 5/5] drm/msm/a6xx: add support for Adreno 660 GPU Jonathan Marek 2021-06-08 17:27 ` Jonathan Marek
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