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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Luis Pires" <luis.pires@eldorado.org.br>,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: [PULL 16/34] tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.h
Date: Fri, 11 Jun 2021 16:41:26 -0700	[thread overview]
Message-ID: <20210611234144.653682-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210611234144.653682-1-richard.henderson@linaro.org>

Remove the ifdef ladder and move each define into the
appropriate header file.

Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.h |  1 +
 tcg/arm/tcg-target.h     |  1 +
 tcg/i386/tcg-target.h    |  2 ++
 tcg/mips/tcg-target.h    |  6 ++++++
 tcg/ppc/tcg-target.h     |  2 ++
 tcg/riscv/tcg-target.h   |  1 +
 tcg/s390/tcg-target.h    |  3 +++
 tcg/sparc/tcg-target.h   |  1 +
 tcg/tci/tcg-target.h     |  1 +
 tcg/region.c             | 33 +++++----------------------------
 10 files changed, 23 insertions(+), 28 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 5ec30dba25..ef55f7c185 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -15,6 +15,7 @@
 
 #define TCG_TARGET_INSN_UNIT_SIZE  4
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24
+#define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
 #undef TCG_TARGET_STACK_GROWSUP
 
 typedef enum {
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index d6222ba2db..57fd0c0c74 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -60,6 +60,7 @@ extern int arm_arch;
 #undef TCG_TARGET_STACK_GROWSUP
 #define TCG_TARGET_INSN_UNIT_SIZE 4
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
+#define MAX_CODE_GEN_BUFFER_SIZE  UINT32_MAX
 
 typedef enum {
     TCG_REG_R0 = 0,
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b693d3692d..ac10066c3e 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -31,9 +31,11 @@
 #ifdef __x86_64__
 # define TCG_TARGET_REG_BITS  64
 # define TCG_TARGET_NB_REGS   32
+# define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
 #else
 # define TCG_TARGET_REG_BITS  32
 # define TCG_TARGET_NB_REGS   24
+# define MAX_CODE_GEN_BUFFER_SIZE  UINT32_MAX
 #endif
 
 typedef enum {
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c2c32fb38f..e81e824cab 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -39,6 +39,12 @@
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
 #define TCG_TARGET_NB_REGS 32
 
+/*
+ * We have a 256MB branch region, but leave room to make sure the
+ * main executable is also within that region.
+ */
+#define MAX_CODE_GEN_BUFFER_SIZE  (128 * MiB)
+
 typedef enum {
     TCG_REG_ZERO = 0,
     TCG_REG_AT,
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index d1339afc66..c13ed5640a 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -27,8 +27,10 @@
 
 #ifdef _ARCH_PPC64
 # define TCG_TARGET_REG_BITS  64
+# define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
 #else
 # define TCG_TARGET_REG_BITS  32
+# define MAX_CODE_GEN_BUFFER_SIZE  (32 * MiB)
 #endif
 
 #define TCG_TARGET_NB_REGS 64
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 727c8df418..87ea94666b 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -34,6 +34,7 @@
 #define TCG_TARGET_INSN_UNIT_SIZE 4
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 20
 #define TCG_TARGET_NB_REGS 32
+#define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
 
 typedef enum {
     TCG_REG_ZERO,
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 641464eea4..b04b72b7eb 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -28,6 +28,9 @@
 #define TCG_TARGET_INSN_UNIT_SIZE 2
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19
 
+/* We have a +- 4GB range on the branches; leave some slop.  */
+#define MAX_CODE_GEN_BUFFER_SIZE  (3 * GiB)
+
 typedef enum TCGReg {
     TCG_REG_R0 = 0,
     TCG_REG_R1,
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index f66f5d07dc..86bb9a2d39 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -30,6 +30,7 @@
 #define TCG_TARGET_INSN_UNIT_SIZE 4
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
 #define TCG_TARGET_NB_REGS 32
+#define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
 
 typedef enum {
     TCG_REG_G0 = 0,
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 52af6d8bc5..d0b5f3fa64 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -43,6 +43,7 @@
 #define TCG_TARGET_INTERPRETER 1
 #define TCG_TARGET_INSN_UNIT_SIZE 1
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
+#define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
 
 #if UINTPTR_MAX == UINT32_MAX
 # define TCG_TARGET_REG_BITS 32
diff --git a/tcg/region.c b/tcg/region.c
index 57069a38ff..13087aa0c9 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@ -401,37 +401,14 @@ static size_t tcg_n_regions(unsigned max_cpus)
 /*
  * Minimum size of the code gen buffer.  This number is randomly chosen,
  * but not so small that we can't have a fair number of TB's live.
+ *
+ * Maximum size, MAX_CODE_GEN_BUFFER_SIZE, is defined in tcg-target.h.
+ * Unless otherwise indicated, this is constrained by the range of
+ * direct branches on the host cpu, as used by the TCG implementation
+ * of goto_tb.
  */
 #define MIN_CODE_GEN_BUFFER_SIZE     (1 * MiB)
 
-/*
- * Maximum size of the code gen buffer we'd like to use.  Unless otherwise
- * indicated, this is constrained by the range of direct branches on the
- * host cpu, as used by the TCG implementation of goto_tb.
- */
-#if defined(__x86_64__)
-# define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
-#elif defined(__sparc__)
-# define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
-#elif defined(__powerpc64__)
-# define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
-#elif defined(__powerpc__)
-# define MAX_CODE_GEN_BUFFER_SIZE  (32 * MiB)
-#elif defined(__aarch64__)
-# define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
-#elif defined(__s390x__)
-  /* We have a +- 4GB range on the branches; leave some slop.  */
-# define MAX_CODE_GEN_BUFFER_SIZE  (3 * GiB)
-#elif defined(__mips__)
-  /*
-   * We have a 256MB branch region, but leave room to make sure the
-   * main executable is also within that region.
-   */
-# define MAX_CODE_GEN_BUFFER_SIZE  (128 * MiB)
-#else
-# define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
-#endif
-
 #if TCG_TARGET_REG_BITS == 32
 #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32 * MiB)
 #ifdef CONFIG_USER_ONLY
-- 
2.25.1



  parent reply	other threads:[~2021-06-11 23:58 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-11 23:41 [PULL 00/34] tcg patch queue Richard Henderson
2021-06-11 23:41 ` [PULL 01/34] meson: Split out tcg/meson.build Richard Henderson
2021-06-11 23:41 ` [PULL 02/34] meson: Split out fpu/meson.build Richard Henderson
2021-06-11 23:41 ` [PULL 03/34] tcg: Re-order tcg_region_init vs tcg_prologue_init Richard Henderson
2021-06-14 14:36   ` Christian Borntraeger
2021-06-11 23:41 ` [PULL 04/34] tcg: Remove error return from tcg_region_initial_alloc__locked Richard Henderson
2021-06-11 23:41 ` [PULL 05/34] tcg: Split out tcg_region_initial_alloc Richard Henderson
2021-06-11 23:41 ` [PULL 06/34] tcg: Split out tcg_region_prologue_set Richard Henderson
2021-06-11 23:41 ` [PULL 07/34] tcg: Split out region.c Richard Henderson
2021-06-11 23:41 ` [PULL 08/34] accel/tcg: Inline cpu_gen_init Richard Henderson
2021-06-11 23:41 ` [PULL 09/34] accel/tcg: Move alloc_code_gen_buffer to tcg/region.c Richard Henderson
2021-06-11 23:41 ` [PULL 10/34] accel/tcg: Rename tcg_init to tcg_init_machine Richard Henderson
2021-06-11 23:41 ` [PULL 11/34] tcg: Create tcg_init Richard Henderson
2021-06-11 23:41 ` [PULL 12/34] accel/tcg: Merge tcg_exec_init into tcg_init_machine Richard Henderson
2021-06-11 23:41 ` [PULL 13/34] accel/tcg: Use MiB in tcg_init_machine Richard Henderson
2021-06-11 23:41 ` [PULL 14/34] accel/tcg: Pass down max_cpus to tcg_init Richard Henderson
2021-06-11 23:41 ` [PULL 15/34] tcg: Introduce tcg_max_ctxs Richard Henderson
2021-06-11 23:41 ` Richard Henderson [this message]
2021-06-11 23:41 ` [PULL 17/34] tcg: Replace region.end with region.total_size Richard Henderson
2021-06-11 23:41 ` [PULL 18/34] tcg: Rename region.start to region.after_prologue Richard Henderson
2021-06-11 23:41 ` [PULL 19/34] tcg: Tidy tcg_n_regions Richard Henderson
2021-06-11 23:41 ` [PULL 20/34] tcg: Tidy split_cross_256mb Richard Henderson
2021-06-11 23:41 ` [PULL 21/34] tcg: Move in_code_gen_buffer and tests to region.c Richard Henderson
2021-06-11 23:41 ` [PULL 22/34] tcg: Allocate code_gen_buffer into struct tcg_region_state Richard Henderson
2021-06-11 23:41 ` [PULL 23/34] tcg: Return the map protection from alloc_code_gen_buffer Richard Henderson
2021-06-11 23:41 ` [PULL 24/34] tcg: Sink qemu_madvise call to common code Richard Henderson
2021-06-11 23:41 ` [PULL 25/34] util/osdep: Add qemu_mprotect_rw Richard Henderson
2021-06-11 23:41 ` [PULL 26/34] tcg: Round the tb_size default from qemu_get_host_physmem Richard Henderson
2021-06-11 23:41 ` [PULL 27/34] tcg: Merge buffer protection and guard page protection Richard Henderson
2021-06-11 23:41 ` [PULL 28/34] tcg: When allocating for !splitwx, begin with PROT_NONE Richard Henderson
2021-06-11 23:41 ` [PULL 29/34] tcg: Move tcg_init_ctx and tcg_ctx from accel/tcg/ Richard Henderson
2021-06-11 23:41 ` [PULL 30/34] tcg: Introduce tcg_remove_ops_after Richard Henderson
2021-06-11 23:41 ` [PULL 31/34] tcg: Fix documentation for tcg_constant_* vs tcg_temp_free_* Richard Henderson
2021-06-11 23:41 ` [PULL 32/34] tcg/arm: Fix tcg_out_op function signature Richard Henderson
2021-06-11 23:41 ` [PULL 33/34] softfloat: Fix tp init in float32_exp2 Richard Henderson
2021-06-11 23:41 ` [PULL 34/34] docs/devel: Explain in more detail the TB chaining mechanisms Richard Henderson
2021-06-13 15:13 ` [PULL 00/34] tcg patch queue Peter Maydell
2021-06-13 17:10   ` Peter Maydell
2021-06-14  1:37     ` Richard Henderson
2021-06-14  9:28       ` Peter Maydell
2021-06-14  9:35       ` Alex Bennée
2021-06-14 15:00         ` Philippe Mathieu-Daudé

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