From: Anusha Srivatsa <anusha.srivatsa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR around cdclk changes to ADL-P
Date: Thu, 17 Jun 2021 14:12:21 -0700 [thread overview]
Message-ID: <20210617211225.13549-2-anusha.srivatsa@intel.com> (raw)
In-Reply-To: <20210617211225.13549-1-anusha.srivatsa@intel.com>
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Only ADL-P platform requires a temporal disabling of PSR for changing the
CDCLK PLL frequency with crawling. Changing the CDCLK PLL frequency on
prior platforms of ADL-P or changing the CDCLK PLL frequency without
crawling on ADL-P don't need to disable of PSR.
Bspec: 49207
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Fixes: 17c1a4b7ac6f ("drm/i915: Disable PSR around cdclk change")
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 613ffcc68eba..6da426d26aac 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1962,10 +1962,18 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ /*
+ * Only ADL-P platform requires a temporal disabling of PSR for changing
+ * the CDCLK PLL frequency with crawling.
+ * Changing the CDCLK PLL frequency on prior platforms of ADL-P or changing
+ * the CDCLK PLL frequency without crawling on ADL-P don't need to disable of PSR.
+ */
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- intel_psr_pause(intel_dp);
+ intel_psr_pause(intel_dp);
+ }
}
/*
@@ -1990,10 +1998,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
}
mutex_unlock(&dev_priv->gmbus_mutex);
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- intel_psr_resume(intel_dp);
+ intel_psr_resume(intel_dp);
+ }
}
if (drm_WARN(&dev_priv->drm,
--
2.32.0
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next prev parent reply other threads:[~2021-06-17 21:12 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 21:12 [Intel-gfx] [PATCH 0/5] Pipe DMC bits + PSR fix Anusha Srivatsa
2021-06-17 21:12 ` Anusha Srivatsa [this message]
2021-06-17 21:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR around cdclk changes to ADL-P Souza, Jose
2021-06-17 21:26 ` Srivatsa, Anusha
2021-06-17 21:30 ` Souza, Jose
2021-06-17 21:12 ` [Intel-gfx] [PATCH 2/5] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
2021-06-17 21:12 ` [Intel-gfx] [PATCH 3/5] drm/i915/xelpd: Pipe A DMC plugging Anusha Srivatsa
2021-06-17 21:12 ` [Intel-gfx] [PATCH 4/5] drm/i915/adl_p: Pipe B DMC Support Anusha Srivatsa
2021-06-17 21:12 ` [Intel-gfx] [PATCH 5/5] drm/i915/adl_p: Load DMC Anusha Srivatsa
2021-06-17 21:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC bits + PSR fix Patchwork
2021-06-17 21:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-17 22:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-17 23:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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