From: Biju Das <biju.das.jz@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
devicetree@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
linux-renesas-soc@vger.kernel.org
Subject: [PATCH 7/7] arm64: dts: renesas: r9a07g044: Add I2C nodes
Date: Fri, 18 Jun 2021 10:58:23 +0100 [thread overview]
Message-ID: <20210618095823.19885-8-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20210618095823.19885-1-biju.das.jz@bp.renesas.com>
Add I2C{0,1,2,3} nodes to RZ/G2 (R9A07G044) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 80 ++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 544f040a4e1d..b573ce88f4da 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -89,6 +89,86 @@
status = "disabled";
};
+ i2c0: i2c@10058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
+ reg = <0 0x10058000 0 0x400>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G044_I2C0_PCLK>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10058400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
+ reg = <0 0x10058400 0 0x400>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G044_I2C1_PCLK>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10058800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
+ reg = <0 0x10058800 0 0x400>;
+ interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G044_I2C2_PCLK>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@10058c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
+ reg = <0 0x10058c00 0 0x400>;
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G044_I2C3_PCLK>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
--
2.17.1
prev parent reply other threads:[~2021-06-18 9:58 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-18 9:58 [PATCH 0/7] Update clock definitions Biju Das
2021-06-18 9:58 ` [PATCH 1/7] dt-bindings: clk: r9a07g044-cpg: " Biju Das
2021-06-21 15:49 ` Geert Uytterhoeven
2021-06-22 9:26 ` Biju Das
2021-06-22 14:56 ` Geert Uytterhoeven
2021-06-23 11:11 ` Biju Das
2021-06-23 11:59 ` Geert Uytterhoeven
2021-06-23 12:33 ` Biju Das
2021-06-18 9:58 ` [PATCH 2/7] drivers: clk: renesas: renesas-rzg2l-cpg: Add multi clock PM support Biju Das
2021-06-22 14:57 ` Geert Uytterhoeven
2021-06-18 9:58 ` [PATCH 3/7] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock entries Biju Das
2021-06-22 15:13 ` Geert Uytterhoeven
2021-06-22 15:50 ` Biju Das
2021-06-23 11:47 ` Biju Das
2021-06-18 9:58 ` [PATCH 4/7] arm64: dts: renesas: r9a07g044: Update SCIF0 clock Biju Das
2021-06-18 9:58 ` [PATCH 5/7] drivers: clk: renesas: r9a07g044-cpg: Add I2C Clocks Biju Das
2021-06-18 9:58 ` [PATCH 6/7] drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks Biju Das
2021-06-18 9:58 ` Biju Das [this message]
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