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From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available
Date: Fri, 18 Jun 2021 17:13:14 +0100	[thread overview]
Message-ID: <20210618161314.723418-2-matthew.auld@intel.com> (raw)
In-Reply-To: <20210618161314.723418-1-matthew.auld@intel.com>

From: Clint Taylor <clinton.a.taylor@intel.com>

Use MCHBAR Gear_type information to compute memory bandwidth available
during MCHBAR calculations.

Tested-by: Swati Sharma <swati2.sharma@intel.com>
Cc: Swati Sharma <swati2.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index f3d8ff4ee0db..38bf24c437d8 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -41,6 +41,9 @@ struct intel_qgv_info {
 #define  DG1_DRAM_T_RP_MASK (0x7F << 0)
 #define  DG1_DRAM_T_RP_SHIFT 0
 
+#define  ICL_GEAR_TYPE_MASK (0x01 << 16)
+#define  ICL_GEAR_TYPE_SHIFT 16
+
 static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
 					  struct intel_qgv_point *sp,
 					  int point)
@@ -55,6 +58,11 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	else
 		dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
 	sp->dclk = dclk_ratio * dclk_reference;
+
+	val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
+	if ((val & ICL_GEAR_TYPE_MASK) >> ICL_GEAR_TYPE_SHIFT)
+		sp->dclk *= 2;
+
 	if (sp->dclk == 0)
 		return -EINVAL;
 
-- 
2.26.3

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  reply	other threads:[~2021-06-18 16:14 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-18 16:13 [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
2021-06-18 16:13 ` Matthew Auld [this message]
2021-06-18 16:18 ` Matthew Auld
2021-06-18 19:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2021-06-18 22:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-06-21  5:46 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
2021-06-21  8:44   ` Matthew Auld
2021-06-21 23:43     ` Lucas De Marchi
2021-06-24  8:31 Matthew Auld
2021-06-24  8:31 ` [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available Matthew Auld

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