From: Christine Zhu <Christine.Zhu@mediatek.com> To: <wim@linux-watchdog.org>, <linux@roeck-us.net>, <robh+dt@kernel.org>, <matthias.bgg@gmail.com> Cc: <srv_heupstream@mediatek.com>, <linux-mediatek@lists.infradead.org>, <linux-arm-kernel@lists.infradead.org>, <inux-kernel@vger.kernel.org>, <linux-watchdog@vger.kernel.org>, <devicetree@vger.kernel.org>, <seiya.wang@mediatek.com>, christine.zhu <Christine.Zhu@mediatek.com> Subject: [v2, 2/3] dt-binding: reset: mt8195: add toprgu reset-controller head file Date: Tue, 22 Jun 2021 23:09:16 +0800 [thread overview] Message-ID: <20210622150917.29137-3-Christine.Zhu@mediatek.com> (raw) In-Reply-To: <20210622150917.29137-1-Christine.Zhu@mediatek.com> From: "christine.zhu" <Christine.Zhu@mediatek.com> Add toprgu reset-controller head file for MT8195 platform Signed-off-by: christine.zhu <Christine.Zhu@mediatek.com> --- .../reset-controller/mt8195-resets.h | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h new file mode 100644 index 000000000000..7ec27a64afc7 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8195-resets.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Crystal Guo <crystal.guo@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Christine Zhu <Christine.Zhu@mediatek.com> To: <wim@linux-watchdog.org>, <linux@roeck-us.net>, <robh+dt@kernel.org>, <matthias.bgg@gmail.com> Cc: <srv_heupstream@mediatek.com>, <linux-mediatek@lists.infradead.org>, <linux-arm-kernel@lists.infradead.org>, <inux-kernel@vger.kernel.org>, <linux-watchdog@vger.kernel.org>, <devicetree@vger.kernel.org>, <seiya.wang@mediatek.com>, christine.zhu <Christine.Zhu@mediatek.com> Subject: [v2, 2/3] dt-binding: reset: mt8195: add toprgu reset-controller head file Date: Tue, 22 Jun 2021 23:09:16 +0800 [thread overview] Message-ID: <20210622150917.29137-3-Christine.Zhu@mediatek.com> (raw) In-Reply-To: <20210622150917.29137-1-Christine.Zhu@mediatek.com> From: "christine.zhu" <Christine.Zhu@mediatek.com> Add toprgu reset-controller head file for MT8195 platform Signed-off-by: christine.zhu <Christine.Zhu@mediatek.com> --- .../reset-controller/mt8195-resets.h | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h new file mode 100644 index 000000000000..7ec27a64afc7 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8195-resets.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Crystal Guo <crystal.guo@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-22 15:10 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-22 15:09 [v2,0/3] watchdog: mt8195: add wdt support Christine Zhu 2021-06-22 15:09 ` Christine Zhu 2021-06-22 15:09 ` Christine Zhu 2021-06-22 15:09 ` [v2,1/3] dt-binding: mediatek: mt8195: update mtk-wdt document Christine Zhu 2021-06-22 15:09 ` Christine Zhu 2021-06-23 3:16 ` Tzung-Bi Shih 2021-06-23 3:16 ` Tzung-Bi Shih 2021-06-23 3:16 ` Tzung-Bi Shih 2021-06-22 15:09 ` Christine Zhu [this message] 2021-06-22 15:09 ` [v2, 2/3] dt-binding: reset: mt8195: add toprgu reset-controller head file Christine Zhu 2021-06-22 15:09 ` [v2,3/3] watchdog: mediatek: mt8195: add wdt support Christine Zhu 2021-06-22 15:09 ` Christine Zhu 2021-06-22 15:17 [v2,0/3] watchdog: " Christine Zhu 2021-06-22 15:17 ` [v2, 2/3] dt-binding: reset: mt8195: add toprgu reset-controller head file Christine Zhu 2021-06-22 15:17 ` Christine Zhu
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