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From: Jonathan Lemon <jonathan.lemon@gmail.com>
To: <tudor.ambarus@microchip.com>, <miquel.raynal@bootlin.com>,
	<richard@nod.at>, <vigneshr@ti.com>
Cc: <linux-mtd@lists.infradead.org>, <kernel-team@fb.com>
Subject: [PATCH] mtd: spi-nor: Enable locking for n25q128a13
Date: Mon, 28 Jun 2021 14:17:29 -0700	[thread overview]
Message-ID: <20210628211729.3625017-1-jonathan.lemon@gmail.com> (raw)

As 4bit block protection patchset for some micron models are merged,
n25q128a13 also uses 4 bit Block Protection scheme, so enable locking
for it. Tested it on n25q128a13, the locking functions work well.

Signed-off-by: Jonathan Lemon <jonathan.lemon@gmail.com>
---
 drivers/mtd/spi-nor/micron-st.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index c224e59820a1..f3d19b716b7b 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -146,7 +146,9 @@ static const struct flash_info st_parts[] = {
 			      SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
 			      SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
 	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256,
-			      SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+			      SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+			      SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+			      SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
 	{ "mt25ql256a",  INFO6(0x20ba19, 0x104400, 64 * 1024,  512,
 			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
 			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-- 
2.30.2


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             reply	other threads:[~2021-06-28 21:18 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-28 21:17 Jonathan Lemon [this message]
2021-07-01 10:13 ` [PATCH] mtd: spi-nor: Enable locking for n25q128a13 Michael Walle
2021-07-01 19:10   ` Jonathan Lemon
2021-10-19 10:15 ` Tudor.Ambarus

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