From: Marek Vasut <marex@denx.de>
To: linux-arm-kernel@lists.infradead.org
Cc: ch@denx.de, Marek Vasut <marex@denx.de>,
Frieder Schrempf <frieder.schrempf@kontron.de>,
Lucas Stach <l.stach@pengutronix.de>,
NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,
Shawn Guo <shawnguo@kernel.org>
Subject: [PATCH 2/2] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
Date: Thu, 1 Jul 2021 01:01:29 +0200 [thread overview]
Message-ID: <20210630230129.237658-2-marex@denx.de> (raw)
In-Reply-To: <20210630230129.237658-1-marex@denx.de>
To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.
Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
---
drivers/soc/imx/gpcv2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 1cf23144d5378..fd1d15c6cf561 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -698,7 +698,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
},
- .pgc = BIT(IMX8MM_PGC_GPU2D),
+ .pgc = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
/* Assert reset, power up domain, deassert reset */
.reset_assert_early = true,
.reset_deassert_early = false,
--
2.30.2
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next prev parent reply other threads:[~2021-06-30 23:04 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-30 23:01 [PATCH 1/2] soc: imx: gpcv2: Turn domain->pgc into bitfield Marek Vasut
2021-06-30 23:01 ` Marek Vasut [this message]
2021-07-01 1:44 ` [PATCH 2/2] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain Peng Fan (OSS)
2021-07-01 1:48 ` [PATCH 1/2] soc: imx: gpcv2: Turn domain->pgc into bitfield Peng Fan (OSS)
2021-07-02 17:02 ` Lucas Stach
2021-07-02 17:48 ` Marek Vasut
2021-07-16 23:34 ` Lucas Stach
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