From: Daniel Vetter <daniel.vetter@ffwll.ch> To: DRI Development <dri-devel@lists.freedesktop.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>, etnaviv@lists.freedesktop.org, Russell King <linux+etnaviv@armlinux.org.uk>, Daniel Vetter <daniel.vetter@intel.com> Subject: [PATCH 3/7] drm/etnaviv: Don't break exclusive fence ordering Date: Tue, 6 Jul 2021 12:12:05 +0200 [thread overview] Message-ID: <20210706101209.3034092-4-daniel.vetter@ffwll.ch> (raw) In-Reply-To: <20210706101209.3034092-1-daniel.vetter@ffwll.ch> There's only one exclusive slot, and we must not break the ordering. A better fix would be to us a dma_fence_chain or _array like e.g. amdgpu now uses, but it probably makes sense to lift this into dma-resv.c code as a proper concept, so that drivers don't have to hack up their own solution each on their own. Hence go with the simple fix for now. Another option is the fence import ioctl from Jason: https://lore.kernel.org/dri-devel/20210610210925.642582-7-jason@jlekstrand.net/ Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Russell King <linux+etnaviv@armlinux.org.uk> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: etnaviv@lists.freedesktop.org --- drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c index 92478a50a580..5c4fed2b7c6a 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c @@ -178,18 +178,20 @@ static int submit_fence_sync(struct etnaviv_gem_submit *submit) for (i = 0; i < submit->nr_bos; i++) { struct etnaviv_gem_submit_bo *bo = &submit->bos[i]; struct dma_resv *robj = bo->obj->base.resv; + bool write = bo->flags & ETNA_SUBMIT_BO_WRITE; - if (!(bo->flags & ETNA_SUBMIT_BO_WRITE)) { + if (!(write)) { ret = dma_resv_reserve_shared(robj, 1); if (ret) return ret; } - if (submit->flags & ETNA_SUBMIT_NO_IMPLICIT) + /* exclusive fences must be ordered */ + if (submit->flags & ETNA_SUBMIT_NO_IMPLICIT && !write) continue; ret = drm_sched_job_await_implicit(&submit->sched_job, &bo->obj->base, - bo->flags & ETNA_SUBMIT_BO_WRITE); + write); if (ret) return ret; } -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Vetter <daniel.vetter@ffwll.ch> To: DRI Development <dri-devel@lists.freedesktop.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>, etnaviv@lists.freedesktop.org, Christian Gmeiner <christian.gmeiner@gmail.com>, Russell King <linux+etnaviv@armlinux.org.uk>, Daniel Vetter <daniel.vetter@intel.com>, Lucas Stach <l.stach@pengutronix.de> Subject: [Intel-gfx] [PATCH 3/7] drm/etnaviv: Don't break exclusive fence ordering Date: Tue, 6 Jul 2021 12:12:05 +0200 [thread overview] Message-ID: <20210706101209.3034092-4-daniel.vetter@ffwll.ch> (raw) In-Reply-To: <20210706101209.3034092-1-daniel.vetter@ffwll.ch> There's only one exclusive slot, and we must not break the ordering. A better fix would be to us a dma_fence_chain or _array like e.g. amdgpu now uses, but it probably makes sense to lift this into dma-resv.c code as a proper concept, so that drivers don't have to hack up their own solution each on their own. Hence go with the simple fix for now. Another option is the fence import ioctl from Jason: https://lore.kernel.org/dri-devel/20210610210925.642582-7-jason@jlekstrand.net/ Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Russell King <linux+etnaviv@armlinux.org.uk> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: etnaviv@lists.freedesktop.org --- drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c index 92478a50a580..5c4fed2b7c6a 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c @@ -178,18 +178,20 @@ static int submit_fence_sync(struct etnaviv_gem_submit *submit) for (i = 0; i < submit->nr_bos; i++) { struct etnaviv_gem_submit_bo *bo = &submit->bos[i]; struct dma_resv *robj = bo->obj->base.resv; + bool write = bo->flags & ETNA_SUBMIT_BO_WRITE; - if (!(bo->flags & ETNA_SUBMIT_BO_WRITE)) { + if (!(write)) { ret = dma_resv_reserve_shared(robj, 1); if (ret) return ret; } - if (submit->flags & ETNA_SUBMIT_NO_IMPLICIT) + /* exclusive fences must be ordered */ + if (submit->flags & ETNA_SUBMIT_NO_IMPLICIT && !write) continue; ret = drm_sched_job_await_implicit(&submit->sched_job, &bo->obj->base, - bo->flags & ETNA_SUBMIT_BO_WRITE); + write); if (ret) return ret; } -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-06 10:12 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-06 10:12 [PATCH 0/7] dma-resv fence DAG fixes Daniel Vetter 2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter 2021-07-06 10:12 ` [PATCH 1/7] drm/msm: Don't break exclusive fence ordering Daniel Vetter 2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter 2021-07-06 10:12 ` Daniel Vetter 2021-07-06 10:12 ` [PATCH 2/7] drm/msm: always wait for the exclusive fence Daniel Vetter 2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter 2021-07-06 10:12 ` Daniel Vetter 2021-07-06 10:12 ` Daniel Vetter [this message] 2021-07-06 10:12 ` [Intel-gfx] [PATCH 3/7] drm/etnaviv: Don't break exclusive fence ordering Daniel Vetter 2021-07-07 8:54 ` Lucas Stach 2021-07-07 8:54 ` [Intel-gfx] " Lucas Stach 2021-07-07 11:37 ` Daniel Vetter 2021-07-07 11:37 ` [Intel-gfx] " Daniel Vetter 2021-07-07 12:31 ` Lucas Stach 2021-07-07 12:31 ` [Intel-gfx] " Lucas Stach 2021-07-07 12:59 ` Daniel Vetter 2021-07-07 12:59 ` [Intel-gfx] " Daniel Vetter 2021-07-06 10:12 ` [PATCH 4/7] drm/i915: delete exclude argument from i915_sw_fence_await_reservation Daniel Vetter 2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter 2021-07-06 10:12 ` [PATCH 5/7] drm/i915: Always wait for the exclusive fence Daniel Vetter 2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter 2021-07-06 12:47 ` Matthew Auld 2021-07-06 12:47 ` Matthew Auld 2021-07-06 12:58 ` Daniel Vetter 2021-07-06 12:58 ` Daniel Vetter 2021-07-06 10:12 ` [PATCH 6/7] drm/i915: Don't break exclusive fence ordering Daniel Vetter 2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter 2021-07-06 10:12 ` [PATCH 7/7] dma-resv: Give the docs a do-over Daniel Vetter 2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter 2021-07-06 10:12 ` Daniel Vetter 2021-07-06 12:34 ` [Intel-gfx] " Matthew Auld 2021-07-06 12:34 ` Matthew Auld 2021-07-06 12:34 ` Matthew Auld 2021-07-06 23:47 ` Jason Ekstrand 2021-07-06 23:47 ` [Intel-gfx] " Jason Ekstrand 2021-07-06 23:47 ` Jason Ekstrand 2021-07-07 8:06 ` [Linaro-mm-sig] " Christian König 2021-07-07 8:06 ` [Intel-gfx] " Christian König 2021-07-07 8:06 ` Christian König 2021-07-07 9:13 ` Daniel Vetter 2021-07-07 9:13 ` [Intel-gfx] " Daniel Vetter 2021-07-07 9:13 ` Daniel Vetter 2021-07-06 10:35 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for dma-resv fence DAG fixes Patchwork
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