From: Leo Yan <leo.yan@linaro.org> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Leo Yan <leo.yan@linaro.org> Subject: [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode Date: Sat, 10 Jul 2021 15:02:05 +0800 [thread overview] Message-ID: <20210710070206.462875-1-leo.yan@linaro.org> (raw) Current code syncs the buffer range is [offset, offset+len), it doesn't consider the case when the trace data is wrapped around, in this case 'offset+len' is bigger than 'etr_buf->size'. Thus it syncs buffer out of the memory buffer, and it also misses to sync buffer from the start of the memory. This patch corrects the memory sync ranges, when detects the wrapping around case, it splits into two chunks: one chunk is the tail of the buffer and another chunk is from the start of the buffer after wrapping around. Signed-off-by: Leo Yan <leo.yan@linaro.org> --- .../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 888b0f929d33..a1afefcbf175 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -780,7 +780,23 @@ static void tmc_etr_sync_sg_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp) else etr_buf->len = ((w_offset < r_offset) ? etr_buf->size : 0) + w_offset - r_offset; - tmc_sg_table_sync_data_range(table, r_offset, etr_buf->len); + + if (r_offset + etr_buf->len > etr_buf->size) { + int len1, len2; + + /* + * If trace data is wrapped around, sync AUX bounce buffer + * for two chunks: "len1" is for the trace date length at + * the tail of bounce buffer, and "len2" is the length from + * the start of the buffer after wrapping around. + */ + len1 = etr_buf->size - r_offset; + len2 = etr_buf->len - len1; + tmc_sg_table_sync_data_range(table, r_offset, len1); + tmc_sg_table_sync_data_range(table, 0, len2); + } else { + tmc_sg_table_sync_data_range(table, r_offset, etr_buf->len); + } } static const struct etr_buf_operations etr_sg_buf_ops = { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Leo Yan <leo.yan@linaro.org> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Leo Yan <leo.yan@linaro.org> Subject: [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode Date: Sat, 10 Jul 2021 15:02:05 +0800 [thread overview] Message-ID: <20210710070206.462875-1-leo.yan@linaro.org> (raw) Current code syncs the buffer range is [offset, offset+len), it doesn't consider the case when the trace data is wrapped around, in this case 'offset+len' is bigger than 'etr_buf->size'. Thus it syncs buffer out of the memory buffer, and it also misses to sync buffer from the start of the memory. This patch corrects the memory sync ranges, when detects the wrapping around case, it splits into two chunks: one chunk is the tail of the buffer and another chunk is from the start of the buffer after wrapping around. Signed-off-by: Leo Yan <leo.yan@linaro.org> --- .../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 888b0f929d33..a1afefcbf175 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -780,7 +780,23 @@ static void tmc_etr_sync_sg_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp) else etr_buf->len = ((w_offset < r_offset) ? etr_buf->size : 0) + w_offset - r_offset; - tmc_sg_table_sync_data_range(table, r_offset, etr_buf->len); + + if (r_offset + etr_buf->len > etr_buf->size) { + int len1, len2; + + /* + * If trace data is wrapped around, sync AUX bounce buffer + * for two chunks: "len1" is for the trace date length at + * the tail of bounce buffer, and "len2" is the length from + * the start of the buffer after wrapping around. + */ + len1 = etr_buf->size - r_offset; + len2 = etr_buf->len - len1; + tmc_sg_table_sync_data_range(table, r_offset, len1); + tmc_sg_table_sync_data_range(table, 0, len2); + } else { + tmc_sg_table_sync_data_range(table, r_offset, etr_buf->len); + } } static const struct etr_buf_operations etr_sg_buf_ops = { -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-07-10 7:02 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-10 7:02 Leo Yan [this message] 2021-07-10 7:02 ` [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode Leo Yan 2021-07-10 7:02 ` [PATCH 2/2] coresight: catu: Correct memory sync ranges in catu mode Leo Yan 2021-07-10 7:02 ` Leo Yan 2021-07-12 10:26 ` Suzuki K Poulose 2021-07-12 10:26 ` Suzuki K Poulose 2021-07-12 10:25 ` [PATCH 1/2] coresight: tmc-etr: Correct memory sync ranges in SG mode Suzuki K Poulose 2021-07-12 10:25 ` Suzuki K Poulose 2021-07-12 11:10 ` Leo Yan 2021-07-12 11:10 ` Leo Yan
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