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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v2 26/55] accel/tcg: Pass MemOpIdx to atomic_trace_*_post
Date: Mon,  2 Aug 2021 18:14:14 -1000	[thread overview]
Message-ID: <20210803041443.55452-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210803041443.55452-1-richard.henderson@linaro.org>

We will shortly use the MemOpIdx directly, but in the meantime
re-compute the trace meminfo.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/atomic_template.h   | 48 +++++++++++++++++------------------
 accel/tcg/atomic_common.c.inc | 30 +++++++++++-----------
 2 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 4230ff2957..c08d859a8a 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -77,15 +77,15 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
                                          PAGE_READ | PAGE_WRITE, retaddr);
     DATA_TYPE ret;
-    uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
 
+    atomic_trace_rmw_pre(env, addr, oi);
 #if DATA_SIZE == 16
     ret = atomic16_cmpxchg(haddr, cmpv, newv);
 #else
     ret = qatomic_cmpxchg__nocheck(haddr, cmpv, newv);
 #endif
     ATOMIC_MMU_CLEANUP;
-    atomic_trace_rmw_post(env, addr, info);
+    atomic_trace_rmw_post(env, addr, oi);
     return ret;
 }
 
@@ -97,11 +97,11 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
                                          PAGE_READ, retaddr);
     DATA_TYPE val;
-    uint16_t info = atomic_trace_ld_pre(env, addr, oi);
 
+    atomic_trace_ld_pre(env, addr, oi);
     val = atomic16_read(haddr);
     ATOMIC_MMU_CLEANUP;
-    atomic_trace_ld_post(env, addr, info);
+    atomic_trace_ld_post(env, addr, oi);
     return val;
 }
 
@@ -110,11 +110,11 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
 {
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
                                          PAGE_WRITE, retaddr);
-    uint16_t info = atomic_trace_st_pre(env, addr, oi);
 
+    atomic_trace_st_pre(env, addr, oi);
     atomic16_set(haddr, val);
     ATOMIC_MMU_CLEANUP;
-    atomic_trace_st_post(env, addr, info);
+    atomic_trace_st_post(env, addr, oi);
 }
 #endif
 #else
@@ -124,11 +124,11 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
                                          PAGE_READ | PAGE_WRITE, retaddr);
     DATA_TYPE ret;
-    uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
 
+    atomic_trace_rmw_pre(env, addr, oi);
     ret = qatomic_xchg__nocheck(haddr, val);
     ATOMIC_MMU_CLEANUP;
-    atomic_trace_rmw_post(env, addr, info);
+    atomic_trace_rmw_post(env, addr, oi);
     return ret;
 }
 
@@ -139,10 +139,10 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,  \
                                          PAGE_READ | PAGE_WRITE, retaddr); \
     DATA_TYPE ret;                                                  \
-    uint16_t info = atomic_trace_rmw_pre(env, addr, oi);            \
+    atomic_trace_rmw_pre(env, addr, oi);                            \
     ret = qatomic_##X(haddr, val);                                  \
     ATOMIC_MMU_CLEANUP;                                             \
-    atomic_trace_rmw_post(env, addr, info);                         \
+    atomic_trace_rmw_post(env, addr, oi);                           \
     return ret;                                                     \
 }
 
@@ -172,7 +172,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
                                           PAGE_READ | PAGE_WRITE, retaddr); \
     XDATA_TYPE cmp, old, new, val = xval;                           \
-    uint16_t info = atomic_trace_rmw_pre(env, addr, oi);            \
+    atomic_trace_rmw_pre(env, addr, oi);                            \
     smp_mb();                                                       \
     cmp = qatomic_read__nocheck(haddr);                             \
     do {                                                            \
@@ -180,7 +180,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
         cmp = qatomic_cmpxchg__nocheck(haddr, old, new);            \
     } while (cmp != old);                                           \
     ATOMIC_MMU_CLEANUP;                                             \
-    atomic_trace_rmw_post(env, addr, info);                         \
+    atomic_trace_rmw_post(env, addr, oi);                           \
     return RET;                                                     \
 }
 
@@ -216,15 +216,15 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
                                          PAGE_READ | PAGE_WRITE, retaddr);
     DATA_TYPE ret;
-    uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
 
+    atomic_trace_rmw_pre(env, addr, oi);
 #if DATA_SIZE == 16
     ret = atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv));
 #else
     ret = qatomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv));
 #endif
     ATOMIC_MMU_CLEANUP;
-    atomic_trace_rmw_post(env, addr, info);
+    atomic_trace_rmw_post(env, addr, oi);
     return BSWAP(ret);
 }
 
@@ -236,11 +236,11 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
                                          PAGE_READ, retaddr);
     DATA_TYPE val;
-    uint16_t info = atomic_trace_ld_pre(env, addr, oi);
 
+    atomic_trace_ld_pre(env, addr, oi);
     val = atomic16_read(haddr);
     ATOMIC_MMU_CLEANUP;
-    atomic_trace_ld_post(env, addr, info);
+    atomic_trace_ld_post(env, addr, oi);
     return BSWAP(val);
 }
 
@@ -249,12 +249,12 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
 {
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
                                          PAGE_WRITE, retaddr);
-    uint16_t info = atomic_trace_st_pre(env, addr, oi);
 
+    atomic_trace_st_pre(env, addr, oi);
     val = BSWAP(val);
     atomic16_set(haddr, val);
     ATOMIC_MMU_CLEANUP;
-    atomic_trace_st_post(env, addr, info);
+    atomic_trace_st_post(env, addr, oi);
 }
 #endif
 #else
@@ -264,11 +264,11 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
                                          PAGE_READ | PAGE_WRITE, retaddr);
     ABI_TYPE ret;
-    uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
 
+    atomic_trace_rmw_pre(env, addr, oi);
     ret = qatomic_xchg__nocheck(haddr, BSWAP(val));
     ATOMIC_MMU_CLEANUP;
-    atomic_trace_rmw_post(env, addr, info);
+    atomic_trace_rmw_post(env, addr, oi);
     return BSWAP(ret);
 }
 
@@ -279,10 +279,10 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,  \
                                          PAGE_READ | PAGE_WRITE, retaddr); \
     DATA_TYPE ret;                                                  \
-    uint16_t info = atomic_trace_rmw_pre(env, addr, oi);            \
+    atomic_trace_rmw_pre(env, addr, oi);                            \
     ret = qatomic_##X(haddr, BSWAP(val));                           \
     ATOMIC_MMU_CLEANUP;                                             \
-    atomic_trace_rmw_post(env, addr, info);                         \
+    atomic_trace_rmw_post(env, addr, oi);                           \
     return BSWAP(ret);                                              \
 }
 
@@ -309,7 +309,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
                                           PAGE_READ | PAGE_WRITE, retaddr); \
     XDATA_TYPE ldo, ldn, old, new, val = xval;                      \
-    uint16_t info = atomic_trace_rmw_pre(env, addr, oi);            \
+    atomic_trace_rmw_pre(env, addr, oi);                            \
     smp_mb();                                                       \
     ldn = qatomic_read__nocheck(haddr);                             \
     do {                                                            \
@@ -317,7 +317,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
         ldn = qatomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new));     \
     } while (ldo != ldn);                                           \
     ATOMIC_MMU_CLEANUP;                                             \
-    atomic_trace_rmw_post(env, addr, info);                         \
+    atomic_trace_rmw_post(env, addr, oi);                           \
     return RET;                                                     \
 }
 
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
index 6019a957b9..db81eb5e66 100644
--- a/accel/tcg/atomic_common.c.inc
+++ b/accel/tcg/atomic_common.c.inc
@@ -13,55 +13,55 @@
  * See the COPYING file in the top-level directory.
  */
 
-static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
-                                     MemOpIdx oi)
+static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
+                                 MemOpIdx oi)
 {
     CPUState *cpu = env_cpu(env);
     uint16_t info = trace_mem_get_info(oi, false);
 
     trace_guest_mem_before_exec(cpu, addr, info);
     trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
-
-    return info;
 }
 
 static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
-                                  uint16_t info)
+                                  MemOpIdx oi)
 {
+    uint16_t info = trace_mem_get_info(oi, false);
+
     qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
     qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST);
 }
 
 #if HAVE_ATOMIC128
-static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
-                                    MemOpIdx oi)
+static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
+                                MemOpIdx oi)
 {
     uint16_t info = trace_mem_get_info(oi, false);
 
     trace_guest_mem_before_exec(env_cpu(env), addr, info);
-
-    return info;
 }
 
 static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
-                                 uint16_t info)
+                                 MemOpIdx oi)
 {
+    uint16_t info = trace_mem_get_info(oi, false);
+
     qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
 }
 
-static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
-                                    MemOpIdx oi)
+static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
+                                MemOpIdx oi)
 {
     uint16_t info = trace_mem_get_info(oi, true);
 
     trace_guest_mem_before_exec(env_cpu(env), addr, info);
-
-    return info;
 }
 
 static void atomic_trace_st_post(CPUArchState *env, target_ulong addr,
-                                 uint16_t info)
+                                 MemOpIdx oi)
 {
+    uint16_t info = trace_mem_get_info(oi, false);
+
     qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
 }
 #endif
-- 
2.25.1



  parent reply	other threads:[~2021-08-03  4:30 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-03  4:13 [PATCH v2 00/55] Unaligned access for user-only Richard Henderson
2021-08-03  4:13 ` [PATCH v2 01/55] hw/core: Make do_unaligned_access noreturn Richard Henderson
2021-08-03 10:01   ` Philippe Mathieu-Daudé
2021-08-03 15:47   ` Alex Bennée
2021-08-03 18:02     ` Richard Henderson
2021-08-03  4:13 ` [PATCH v2 02/55] hw/core: Make do_unaligned_access available to user-only Richard Henderson
2021-08-03  9:59   ` Philippe Mathieu-Daudé
2021-08-03 15:51   ` Alex Bennée
2021-08-03  4:13 ` [PATCH v2 03/55] target/alpha: Implement do_unaligned_access for user-only Richard Henderson
2021-08-18  8:45   ` Philippe Mathieu-Daudé
2021-08-03  4:13 ` [PATCH v2 04/55] target/arm: " Richard Henderson
2021-08-03  4:13 ` [PATCH v2 05/55] target/hppa: " Richard Henderson
2021-08-18  8:46   ` Philippe Mathieu-Daudé
2021-08-03  4:13 ` [PATCH v2 06/55] target/microblaze: Do not set MO_ALIGN " Richard Henderson
2021-08-04  9:25   ` Edgar E. Iglesias
2021-08-03  4:13 ` [PATCH v2 07/55] target/mips: Implement do_unaligned_access " Richard Henderson
2021-08-19 19:33   ` Peter Maydell
2021-08-03  4:13 ` [PATCH v2 08/55] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-08-03  4:13 ` [PATCH v2 09/55] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-08-03  4:13 ` [PATCH v2 10/55] target/ppc: Implement do_unaligned_access for user-only Richard Henderson
2021-08-03  4:13 ` [PATCH v2 11/55] target/riscv: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 12/55] target/s390x: " Richard Henderson
2021-08-18  8:47   ` Philippe Mathieu-Daudé
2021-08-03  4:14 ` [PATCH v2 13/55] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-08-03  4:14 ` [PATCH v2 14/55] target/sh4: Implement do_unaligned_access for user-only Richard Henderson
2021-08-03  4:14 ` [PATCH v2 15/55] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-08-18  8:36   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 16/55] target/sparc: Split out build_sfsr Richard Henderson
2021-08-18  8:38   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 17/55] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-08-18  8:47   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 18/55] target/sparc: Implement do_unaligned_access for user-only Richard Henderson
2021-08-18  8:48   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 19/55] target/xtensa: " Richard Henderson
2021-08-03  5:38   ` Max Filippov
2021-08-18  8:48   ` Philippe Mathieu-Daudé
2021-08-03  4:14 ` [PATCH v2 20/55] accel/tcg: Report unaligned atomics " Richard Henderson
2021-08-03 15:54   ` Alex Bennée
2021-08-18  8:51   ` Philippe Mathieu-Daudé
2021-08-18 17:47     ` Richard Henderson
2021-08-03  4:14 ` [PATCH v2 21/55] accel/tcg: Drop signness in tracing in cputlb.c Richard Henderson
2021-08-03 15:58   ` Alex Bennée
2021-08-03  4:14 ` [PATCH v2 22/55] tcg: Expand MO_SIZE to 3 bits Richard Henderson
2021-08-03  4:14 ` [PATCH v2 23/55] tcg: Rename TCGMemOpIdx to MemOpIdx Richard Henderson
2021-08-03  4:14 ` [PATCH v2 24/55] tcg: Split out MemOpIdx to exec/memopidx.h Richard Henderson
2021-08-03  4:14 ` [PATCH v2 25/55] trace/mem: Pass MemOpIdx to trace_mem_get_info Richard Henderson
2021-08-03  4:14 ` Richard Henderson [this message]
2021-08-03  4:14 ` [PATCH v2 27/55] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb Richard Henderson
2021-08-03  4:14 ` [PATCH v2 28/55] trace: Split guest_mem_before Richard Henderson
2021-08-18  8:58   ` Philippe Mathieu-Daudé
2021-08-03  4:14 ` [PATCH v2 29/55] target/arm: Use MO_128 for 16 byte atomics Richard Henderson
2021-08-03  4:14 ` [PATCH v2 30/55] target/i386: " Richard Henderson
2021-08-18  8:59   ` Philippe Mathieu-Daudé
2021-08-03  4:14 ` [PATCH v2 31/55] target/ppc: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 32/55] target/s390x: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 33/55] target/hexagon: Implement cpu_mmu_index Richard Henderson
2021-08-03  4:14 ` [PATCH v2 34/55] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Richard Henderson
2021-08-18  9:01   ` Philippe Mathieu-Daudé
2021-08-18 17:50     ` Richard Henderson
2021-08-03  4:14 ` [PATCH v2 35/55] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
2021-08-03  4:14 ` [PATCH v2 36/55] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
2021-08-03  4:14 ` [PATCH v2 37/55] target/mips: Use 8-byte memory ops " Richard Henderson
2021-08-18  9:21   ` Philippe Mathieu-Daudé
2021-08-18 17:55     ` Richard Henderson
2021-08-03  4:14 ` [PATCH v2 38/55] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
2021-08-03 11:44   ` David Hildenbrand
2021-08-03  4:14 ` [PATCH v2 39/55] target/sparc: " Richard Henderson
2021-08-03  9:55   ` Philippe Mathieu-Daudé
2021-08-18  8:51   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 40/55] target/arm: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 41/55] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
2021-08-03  4:14 ` [PATCH v2 42/55] tcg: Add helper_unaligned_mmu for user-only sigbus Richard Henderson
2021-08-03  4:14 ` [PATCH v2 43/55] tcg/i386: Support raising sigbus for user-only Richard Henderson
2021-08-03  4:14 ` [PATCH v2 44/55] tests/tcg/multiarch: Add sigbus.c Richard Henderson
2021-08-03  4:14 ` [PATCH v2 45/55] linux-user: Split out do_prctl and subroutines Richard Henderson
2021-08-03  4:14 ` [PATCH v2 46/55] linux-user: Disable more prctl subcodes Richard Henderson
2021-08-03  4:14 ` [PATCH v2 47/55] hw/core/cpu: Re-sort the non-pointers to the end of CPUClass Richard Henderson
2021-08-03  4:14 ` [PATCH v2 48/55] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
2021-08-03  4:14 ` [PATCH v2 49/55] hw/core/cpu: Move cpu properties to cpu-sysemu.c Richard Henderson
2021-08-03  4:14 ` [PATCH v2 50/55] hw/core/cpu: Add prctl-unalign-sigbus property for user-only Richard Henderson
2021-08-03  4:14 ` [PATCH v2 51/55] target/alpha: Reorg fp memory operations Richard Henderson
2021-08-03  4:14 ` [PATCH v2 52/55] target/alpha: Reorg integer " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 53/55] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
2021-08-03  4:14 ` [PATCH v2 54/55] target/hppa: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 55/55] target/sh4: " Richard Henderson

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