From: Vineet Gupta <vgupta@kernel.org> To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Anshuman Khandual <anshuman.khandual@arm.com>, Mike Rapoport <rppt@kernel.org>, Vineet Gupta <vgupta@kernel.org> Subject: [PATCH v2 15/19] ARC: mm: hack to allow 2 level build with 4 level code Date: Thu, 12 Aug 2021 16:37:49 -0700 [thread overview] Message-ID: <20210812233753.104217-16-vgupta@kernel.org> (raw) In-Reply-To: <20210812233753.104217-1-vgupta@kernel.org> PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-* but only for !__ASSEMBLY__ tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs for CONFIG_PGTABLE_LEVEL={2,3} and works for 4. So add a workaround local to tlbex.S - the proper fix is to change asm-generic/pgtable-* headers to expose the defines for __ASSEMBLY__ too Signed-off-by: Vineet Gupta <vgupta@kernel.org> --- arch/arc/mm/tlbex.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 0b4bb62fa0ab..c4a5f16444ce 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -145,6 +145,14 @@ ex_saved_reg1: ;TLB Miss handling Code ;============================================================================ +#ifndef PMD_SHIFT +#define PMD_SHIFT PUD_SHIFT +#endif + +#ifndef PUD_SHIFT +#define PUD_SHIFT PGDIR_SHIFT +#endif + ;----------------------------------------------------------------------------- ; This macro does the page-table lookup for the faulting address. ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Vineet Gupta <vgupta@kernel.org> To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Anshuman Khandual <anshuman.khandual@arm.com>, Mike Rapoport <rppt@kernel.org>, Vineet Gupta <vgupta@kernel.org> Subject: [PATCH v2 15/19] ARC: mm: hack to allow 2 level build with 4 level code Date: Thu, 12 Aug 2021 16:37:49 -0700 [thread overview] Message-ID: <20210812233753.104217-16-vgupta@kernel.org> (raw) In-Reply-To: <20210812233753.104217-1-vgupta@kernel.org> PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-* but only for !__ASSEMBLY__ tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs for CONFIG_PGTABLE_LEVEL={2,3} and works for 4. So add a workaround local to tlbex.S - the proper fix is to change asm-generic/pgtable-* headers to expose the defines for __ASSEMBLY__ too Signed-off-by: Vineet Gupta <vgupta@kernel.org> --- arch/arc/mm/tlbex.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 0b4bb62fa0ab..c4a5f16444ce 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -145,6 +145,14 @@ ex_saved_reg1: ;TLB Miss handling Code ;============================================================================ +#ifndef PMD_SHIFT +#define PMD_SHIFT PUD_SHIFT +#endif + +#ifndef PUD_SHIFT +#define PUD_SHIFT PGDIR_SHIFT +#endif + ;----------------------------------------------------------------------------- ; This macro does the page-table lookup for the faulting address. ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address -- 2.25.1 _______________________________________________ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
next prev parent reply other threads:[~2021-08-12 23:38 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-12 23:37 [PATCH v2 00/19] ARC mm updates: support 3/4 levels and asm-generic/pgalloc Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 01/19] ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-15 9:27 ` Mike Rapoport 2021-08-15 9:27 ` Mike Rapoport 2021-08-16 19:45 ` Vineet Gupta 2021-08-16 19:45 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 02/19] ARC: mm: remove tlb paranoid code Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 03/19] ARC: mm: move mmu/cache externs out to setup.h Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-15 9:27 ` Mike Rapoport 2021-08-15 9:27 ` Mike Rapoport 2021-08-16 19:47 ` Vineet Gupta 2021-08-16 19:47 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 04/19] ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 05/19] ARC: mm: Enable STRICT_MM_TYPECHECKS Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 06/19] ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 07/19] ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set) Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 08/19] ARC: mm: switch pgtable_t back to struct page * Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-13 10:45 ` kernel test robot 2021-08-13 10:45 ` kernel test robot 2021-08-13 10:45 ` kernel test robot 2021-08-13 14:25 ` Vineet Gupta 2021-08-13 14:25 ` Vineet Gupta 2021-08-13 14:25 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 09/19] ARC: mm: switch to asm-generic/pgalloc.h Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 10/19] ARC: mm: non-functional code cleanup ahead of 3 levels Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 11/19] ARC: mm: move MMU specific bits out of ASID allocator Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 12/19] ARC: mm: move MMU specific bits out of entry code Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 13/19] ARC: mm: disintegrate mmu.h (arcv2 bits out) Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-13 4:01 ` kernel test robot 2021-08-13 4:01 ` kernel test robot 2021-08-13 4:01 ` kernel test robot 2021-08-13 14:48 ` Vineet Gupta 2021-08-13 14:48 ` Vineet Gupta 2021-08-13 14:48 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 14/19] ARC: mm: disintegrate pgtable.h into levels and flags Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta [this message] 2021-08-12 23:37 ` [PATCH v2 15/19] ARC: mm: hack to allow 2 level build with 4 level code Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 16/19] ARC: mm: support 3 levels of page tables Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-15 9:27 ` Mike Rapoport 2021-08-15 9:27 ` Mike Rapoport 2021-08-16 19:53 ` Vineet Gupta 2021-08-16 19:53 ` Vineet Gupta 2021-08-17 5:03 ` Mike Rapoport 2021-08-17 5:03 ` Mike Rapoport 2021-08-12 23:37 ` [PATCH v2 17/19] ARC: mm: support 4 " Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 18/19] ARC: mm: vmalloc sync from kernel to user table to update PMD Vineet Gupta 2021-08-12 23:37 ` Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 19/19] ARC: mm: introduce _PAGE_TABLE to explicitly link pgd,pud,pmd entries Vineet Gupta 2021-08-12 23:37 ` [PATCH v2 19/19] ARC: mm: introduce _PAGE_TABLE to explicitly link pgd, pud, pmd entries Vineet Gupta 2021-08-15 9:26 ` [PATCH v2 00/19] ARC mm updates: support 3/4 levels and asm-generic/pgalloc Mike Rapoport 2021-08-15 9:26 ` Mike Rapoport 2021-08-16 19:58 ` Vineet Gupta 2021-08-16 19:58 ` Vineet Gupta 2021-08-17 5:04 ` Mike Rapoport 2021-08-17 5:04 ` Mike Rapoport
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