From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org Subject: [PATCH v3 00/21] target/riscv: Use tcg_constant_* Date: Wed, 18 Aug 2021 23:04:41 -1000 [thread overview] Message-ID: <20210819090502.428068-1-richard.henderson@linaro.org> (raw) Replace use of tcg_const_*, which makes a copy into a temp which must be freed, with direct use of the constant. Reorg handling of $zero, with different accessors for source and destination. Reorg handling of csrs, passing the actual write_mask instead of a regno. Use more helpers for RVH expansion. Patches lacking review: 02-target-riscv-Clean-up-division-helpers.patch 10-target-riscv-Add-DisasExtend-to-gen_unary.patch 12-target-riscv-Add-gen_greviw.patch 17-target-riscv-Use-gen_shift_imm_fn-for-slli_uw.patch 21-target-riscv-Use-get-dest-_gpr-for-RVV.patch Though I guess patch 12 could be dropped, given what I learned today about the Zbb 1.0.0 public review document. Changes for v3: * Fix an introduced remainder bug (bin meng), and remove one extra movcond from rem/remu. * Do not zero DisasContext on allocation (bin meng). Changes for v2: * Retain the requirement to call gen_set_gpr. * Add DisasExtend as an argument to get_gpr, and ctx->w as a member of DisasContext. This should help in implementing UXL, where we should be able to set ctx->w for all insns, but there is certainly more required for that. r~ Richard Henderson (21): target/riscv: Use tcg_constant_* target/riscv: Clean up division helpers target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr target/riscv: Introduce DisasExtend and new helpers target/riscv: Add DisasExtend to gen_arith* target/riscv: Remove gen_arith_div* target/riscv: Use gen_arith for mulh and mulhu target/riscv: Move gen_* helpers for RVM target/riscv: Move gen_* helpers for RVB target/riscv: Add DisasExtend to gen_unary target/riscv: Use DisasExtend in shift operations target/riscv: Add gen_greviw target/riscv: Use get_gpr in branches target/riscv: Use {get,dest}_gpr for integer load/store target/riscv: Reorg csr instructions target/riscv: Use {get,dest}_gpr for RVA target/riscv: Use gen_shift_imm_fn for slli_uw target/riscv: Use {get,dest}_gpr for RVF target/riscv: Use {get,dest}_gpr for RVD target/riscv: Tidy trans_rvh.c.inc target/riscv: Use {get,dest}_gpr for RVV target/riscv/helper.h | 6 +- target/riscv/insn32.decode | 1 + target/riscv/op_helper.c | 18 +- target/riscv/translate.c | 701 ++++++------------------ target/riscv/insn_trans/trans_rva.c.inc | 51 +- target/riscv/insn_trans/trans_rvb.c.inc | 382 ++++++++++--- target/riscv/insn_trans/trans_rvd.c.inc | 127 +++-- target/riscv/insn_trans/trans_rvf.c.inc | 149 +++-- target/riscv/insn_trans/trans_rvh.c.inc | 266 ++------- target/riscv/insn_trans/trans_rvi.c.inc | 360 ++++++------ target/riscv/insn_trans/trans_rvm.c.inc | 179 ++++-- target/riscv/insn_trans/trans_rvv.c.inc | 151 ++--- 12 files changed, 1062 insertions(+), 1329 deletions(-) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, bin.meng@windriver.com, alistair.francis@wdc.com Subject: [PATCH v3 00/21] target/riscv: Use tcg_constant_* Date: Wed, 18 Aug 2021 23:04:41 -1000 [thread overview] Message-ID: <20210819090502.428068-1-richard.henderson@linaro.org> (raw) Replace use of tcg_const_*, which makes a copy into a temp which must be freed, with direct use of the constant. Reorg handling of $zero, with different accessors for source and destination. Reorg handling of csrs, passing the actual write_mask instead of a regno. Use more helpers for RVH expansion. Patches lacking review: 02-target-riscv-Clean-up-division-helpers.patch 10-target-riscv-Add-DisasExtend-to-gen_unary.patch 12-target-riscv-Add-gen_greviw.patch 17-target-riscv-Use-gen_shift_imm_fn-for-slli_uw.patch 21-target-riscv-Use-get-dest-_gpr-for-RVV.patch Though I guess patch 12 could be dropped, given what I learned today about the Zbb 1.0.0 public review document. Changes for v3: * Fix an introduced remainder bug (bin meng), and remove one extra movcond from rem/remu. * Do not zero DisasContext on allocation (bin meng). Changes for v2: * Retain the requirement to call gen_set_gpr. * Add DisasExtend as an argument to get_gpr, and ctx->w as a member of DisasContext. This should help in implementing UXL, where we should be able to set ctx->w for all insns, but there is certainly more required for that. r~ Richard Henderson (21): target/riscv: Use tcg_constant_* target/riscv: Clean up division helpers target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr target/riscv: Introduce DisasExtend and new helpers target/riscv: Add DisasExtend to gen_arith* target/riscv: Remove gen_arith_div* target/riscv: Use gen_arith for mulh and mulhu target/riscv: Move gen_* helpers for RVM target/riscv: Move gen_* helpers for RVB target/riscv: Add DisasExtend to gen_unary target/riscv: Use DisasExtend in shift operations target/riscv: Add gen_greviw target/riscv: Use get_gpr in branches target/riscv: Use {get,dest}_gpr for integer load/store target/riscv: Reorg csr instructions target/riscv: Use {get,dest}_gpr for RVA target/riscv: Use gen_shift_imm_fn for slli_uw target/riscv: Use {get,dest}_gpr for RVF target/riscv: Use {get,dest}_gpr for RVD target/riscv: Tidy trans_rvh.c.inc target/riscv: Use {get,dest}_gpr for RVV target/riscv/helper.h | 6 +- target/riscv/insn32.decode | 1 + target/riscv/op_helper.c | 18 +- target/riscv/translate.c | 701 ++++++------------------ target/riscv/insn_trans/trans_rva.c.inc | 51 +- target/riscv/insn_trans/trans_rvb.c.inc | 382 ++++++++++--- target/riscv/insn_trans/trans_rvd.c.inc | 127 +++-- target/riscv/insn_trans/trans_rvf.c.inc | 149 +++-- target/riscv/insn_trans/trans_rvh.c.inc | 266 ++------- target/riscv/insn_trans/trans_rvi.c.inc | 360 ++++++------ target/riscv/insn_trans/trans_rvm.c.inc | 179 ++++-- target/riscv/insn_trans/trans_rvv.c.inc | 151 ++--- 12 files changed, 1062 insertions(+), 1329 deletions(-) -- 2.25.1
next reply other threads:[~2021-08-19 9:06 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-19 9:04 Richard Henderson [this message] 2021-08-19 9:04 ` [PATCH v3 00/21] target/riscv: Use tcg_constant_* Richard Henderson 2021-08-19 9:04 ` [PATCH v3 01/21] " Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 02/21] target/riscv: Clean up division helpers Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 11:00 ` Bin Meng 2021-08-19 11:00 ` Bin Meng 2021-08-19 17:23 ` Richard Henderson 2021-08-19 17:23 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 04/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 11:01 ` Bin Meng 2021-08-19 11:01 ` Bin Meng 2021-08-19 9:04 ` [PATCH v3 05/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 06/21] target/riscv: Remove gen_arith_div* Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 07/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 08/21] target/riscv: Move gen_* helpers for RVM Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-20 1:35 ` Alistair Francis 2021-08-20 1:35 ` Alistair Francis 2021-08-19 9:04 ` [PATCH v3 09/21] target/riscv: Move gen_* helpers for RVB Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 10/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 11/21] target/riscv: Use DisasExtend in shift operations Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 12/21] target/riscv: Add gen_greviw Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 13/21] target/riscv: Use get_gpr in branches Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 15/21] target/riscv: Reorg csr instructions Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:04 ` [PATCH v3 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson 2021-08-19 9:04 ` Richard Henderson 2021-08-19 9:05 ` [PATCH v3 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson 2021-08-19 9:05 ` Richard Henderson 2021-08-19 9:05 ` [PATCH v3 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson 2021-08-19 9:05 ` Richard Henderson 2021-08-19 9:05 ` [PATCH v3 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson 2021-08-19 9:05 ` Richard Henderson
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