From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
To: heiko@sntech.de, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, vkoul@kernel.org,
michael.riesch@wolfvision.net,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kishon@ti.com, p.zabel@pengutronix.de,
Yifeng Zhao <yifeng.zhao@rock-chips.com>
Subject: [PATCH v1 1/3] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
Date: Thu, 26 Aug 2021 20:38:42 +0800 [thread overview]
Message-ID: <20210826123844.8464-2-yifeng.zhao@rock-chips.com> (raw)
In-Reply-To: <20210826123844.8464-1-yifeng.zhao@rock-chips.com>
Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
---
.../phy/phy-rockchip-naneng-combphy.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
new file mode 100644
index 000000000000..69908614609c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-naneng-combphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: reference clock
+ - description: apb clock
+ - description: pipe clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ref
+ - const: apb
+ - const: pipe
+
+ '#phy-cells':
+ const: 1
+
+ resets:
+ minItems: 1
+ items:
+ - description: exclusive apb reset line
+ - description: exclusive PHY reset line
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: combphy-apb
+ - const: combphy
+
+ rockchip,pipe-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional phy settings are access through GRF regs.
+
+ rockchip,pipe-phy-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional pipe settings are access through GRF regs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#phy-cells'
+ - resets
+ - reset-names
+ - rockchip,pipe-grf
+ - rockchip,pipe-phy-grf
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/clock/rk3568-cru.h>
+
+ pipegrf: syscon@fdc50000 {
+ compatible = "rockchip,rk3568-pipegrf", "syscon";
+ reg = <0xfdc50000 0x1000>;
+ };
+
+ pipe_phy_grf0: syscon@fdc70000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0xfdc70000 0x1000>;
+ };
+
+ combphy0_us: phy@fe820000 {
+ compatible = "rockchip,rk3568-naneng-combphy";
+ reg = <0xfe820000 0x100>;
+ #phy-cells = <1>;
+ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ };
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
To: heiko@sntech.de, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, vkoul@kernel.org,
michael.riesch@wolfvision.net,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kishon@ti.com, p.zabel@pengutronix.de,
Yifeng Zhao <yifeng.zhao@rock-chips.com>
Subject: [PATCH v1 1/3] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
Date: Thu, 26 Aug 2021 20:38:42 +0800 [thread overview]
Message-ID: <20210826123844.8464-2-yifeng.zhao@rock-chips.com> (raw)
In-Reply-To: <20210826123844.8464-1-yifeng.zhao@rock-chips.com>
Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
---
.../phy/phy-rockchip-naneng-combphy.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
new file mode 100644
index 000000000000..69908614609c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-naneng-combphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: reference clock
+ - description: apb clock
+ - description: pipe clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ref
+ - const: apb
+ - const: pipe
+
+ '#phy-cells':
+ const: 1
+
+ resets:
+ minItems: 1
+ items:
+ - description: exclusive apb reset line
+ - description: exclusive PHY reset line
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: combphy-apb
+ - const: combphy
+
+ rockchip,pipe-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional phy settings are access through GRF regs.
+
+ rockchip,pipe-phy-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional pipe settings are access through GRF regs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#phy-cells'
+ - resets
+ - reset-names
+ - rockchip,pipe-grf
+ - rockchip,pipe-phy-grf
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/clock/rk3568-cru.h>
+
+ pipegrf: syscon@fdc50000 {
+ compatible = "rockchip,rk3568-pipegrf", "syscon";
+ reg = <0xfdc50000 0x1000>;
+ };
+
+ pipe_phy_grf0: syscon@fdc70000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0xfdc70000 0x1000>;
+ };
+
+ combphy0_us: phy@fe820000 {
+ compatible = "rockchip,rk3568-naneng-combphy";
+ reg = <0xfe820000 0x100>;
+ #phy-cells = <1>;
+ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ };
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
To: heiko@sntech.de, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, vkoul@kernel.org,
michael.riesch@wolfvision.net,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kishon@ti.com, p.zabel@pengutronix.de,
Yifeng Zhao <yifeng.zhao@rock-chips.com>
Subject: [PATCH v1 1/3] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
Date: Thu, 26 Aug 2021 20:38:42 +0800 [thread overview]
Message-ID: <20210826123844.8464-2-yifeng.zhao@rock-chips.com> (raw)
In-Reply-To: <20210826123844.8464-1-yifeng.zhao@rock-chips.com>
Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
---
.../phy/phy-rockchip-naneng-combphy.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
new file mode 100644
index 000000000000..69908614609c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-naneng-combphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: reference clock
+ - description: apb clock
+ - description: pipe clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ref
+ - const: apb
+ - const: pipe
+
+ '#phy-cells':
+ const: 1
+
+ resets:
+ minItems: 1
+ items:
+ - description: exclusive apb reset line
+ - description: exclusive PHY reset line
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: combphy-apb
+ - const: combphy
+
+ rockchip,pipe-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional phy settings are access through GRF regs.
+
+ rockchip,pipe-phy-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional pipe settings are access through GRF regs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#phy-cells'
+ - resets
+ - reset-names
+ - rockchip,pipe-grf
+ - rockchip,pipe-phy-grf
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/clock/rk3568-cru.h>
+
+ pipegrf: syscon@fdc50000 {
+ compatible = "rockchip,rk3568-pipegrf", "syscon";
+ reg = <0xfdc50000 0x1000>;
+ };
+
+ pipe_phy_grf0: syscon@fdc70000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0xfdc70000 0x1000>;
+ };
+
+ combphy0_us: phy@fe820000 {
+ compatible = "rockchip,rk3568-naneng-combphy";
+ reg = <0xfe820000 0x100>;
+ #phy-cells = <1>;
+ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ };
--
2.17.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
To: heiko@sntech.de, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, vkoul@kernel.org,
michael.riesch@wolfvision.net,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kishon@ti.com, p.zabel@pengutronix.de,
Yifeng Zhao <yifeng.zhao@rock-chips.com>
Subject: [PATCH v1 1/3] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
Date: Thu, 26 Aug 2021 20:38:42 +0800 [thread overview]
Message-ID: <20210826123844.8464-2-yifeng.zhao@rock-chips.com> (raw)
In-Reply-To: <20210826123844.8464-1-yifeng.zhao@rock-chips.com>
Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
---
.../phy/phy-rockchip-naneng-combphy.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
new file mode 100644
index 000000000000..69908614609c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-naneng-combphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: reference clock
+ - description: apb clock
+ - description: pipe clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ref
+ - const: apb
+ - const: pipe
+
+ '#phy-cells':
+ const: 1
+
+ resets:
+ minItems: 1
+ items:
+ - description: exclusive apb reset line
+ - description: exclusive PHY reset line
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: combphy-apb
+ - const: combphy
+
+ rockchip,pipe-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional phy settings are access through GRF regs.
+
+ rockchip,pipe-phy-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional pipe settings are access through GRF regs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#phy-cells'
+ - resets
+ - reset-names
+ - rockchip,pipe-grf
+ - rockchip,pipe-phy-grf
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/clock/rk3568-cru.h>
+
+ pipegrf: syscon@fdc50000 {
+ compatible = "rockchip,rk3568-pipegrf", "syscon";
+ reg = <0xfdc50000 0x1000>;
+ };
+
+ pipe_phy_grf0: syscon@fdc70000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0xfdc70000 0x1000>;
+ };
+
+ combphy0_us: phy@fe820000 {
+ compatible = "rockchip,rk3568-naneng-combphy";
+ reg = <0xfe820000 0x100>;
+ #phy-cells = <1>;
+ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ };
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-26 12:39 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-26 12:38 [PATCH v1 0/3] Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao [this message]
2021-08-26 12:38 ` [PATCH v1 1/3] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao
2021-08-26 13:26 ` Rob Herring
2021-08-26 13:26 ` Rob Herring
2021-08-26 13:26 ` Rob Herring
2021-08-26 13:26 ` Rob Herring
2021-08-26 12:38 ` [PATCH v1 2/3] phy/rockchip: add naneng combo phy for RK3568 Yifeng Zhao
2021-10-12 7:36 ` Nicolas Frattaroli
2021-10-12 7:36 ` Nicolas Frattaroli
2021-10-12 7:36 ` Nicolas Frattaroli
2021-10-12 7:36 ` Nicolas Frattaroli
2021-08-26 12:38 ` [PATCH v1 3/3] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao
2021-08-26 12:38 ` Yifeng Zhao
2021-10-12 11:24 ` Nicolas Frattaroli
2021-10-12 11:24 ` Nicolas Frattaroli
2021-10-12 11:24 ` Nicolas Frattaroli
2021-10-12 11:24 ` Nicolas Frattaroli
2021-09-17 17:21 ` [PATCH v1 0/3] Peter Geis
2021-09-17 17:21 ` Peter Geis
2021-09-17 17:21 ` Peter Geis
2021-09-17 17:21 ` Peter Geis
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