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From: rashmi.a@intel.com
To: michal.simek@xilinx.com, ulf.hansson@linaro.org,
	linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kishon@ti.com, vkoul@kernel.org,
	andriy.shevchenko@linux.intel.com, linux-phy@lists.infradead.org
Cc: mgross@linux.intel.com, kris.pan@linux.intel.com,
	furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com,
	adrian.hunter@intel.com, mahesh.r.vaidya@intel.com,
	nandhini.srikandan@intel.com, rashmi.a@intel.com
Subject: [PATCH v2 2/4] dt-bindings: mmc: Add bindings for Intel Thunder Bay SoC
Date: Sun, 29 Aug 2021 23:54:41 +0530	[thread overview]
Message-ID: <20210829182443.30802-3-rashmi.a@intel.com> (raw)
In-Reply-To: <20210829182443.30802-1-rashmi.a@intel.com>

From: Rashmi A <rashmi.a@intel.com>

Add documentation for Arasan SDHCI controller in Thunder Bay SOC.

Signed-off-by: Rashmi A <rashmi.a@intel.com>
---
 .../devicetree/bindings/mmc/arasan,sdhci.yaml | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
index 37a5fe7b26dc..23abb7e8b9d8 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
@@ -88,6 +88,12 @@ properties:
         description:
           For this device it is strongly suggested to include
           arasan,soc-ctl-syscon.
+      - items:
+          - const: intel,thunderbay-sdhci-5.1   # Intel Thunder Bay eMMC PHY
+          - const: arasan,sdhci-5.1
+        description:
+          For this device it is strongly suggested to include
+          clock-output-names and '#clock-cells'.
 
   reg:
     maxItems: 1
@@ -301,3 +307,22 @@ examples:
                    <&scmi_clk KEEM_BAY_PSS_SD0>;
           arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
     };
+
+  - |
+    #define EMMC_XIN_CLK
+    #define EMMC_AXI_CLK
+    #define TBH_PSS_EMMC_RST_N
+    mmc@80420000 {
+          compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
+          interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
+          reg = <0x80420000 0x400>;
+          clocks = <&scmi_clk EMMC_XIN_CLK>,
+                   <&scmi_clk EMMC_AXI_CLK>;
+          clock-names = "clk_xin", "clk_ahb";
+          phys = <&emmc_phy>;
+          phy-names = "phy_arasan";
+          assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
+          clock-output-names = "emmc_cardclock";
+          resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
+          #clock-cells = <0x0>;
+    };
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: rashmi.a@intel.com
To: michal.simek@xilinx.com, ulf.hansson@linaro.org,
	linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kishon@ti.com, vkoul@kernel.org,
	andriy.shevchenko@linux.intel.com, linux-phy@lists.infradead.org
Cc: mgross@linux.intel.com, kris.pan@linux.intel.com,
	furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com,
	adrian.hunter@intel.com, mahesh.r.vaidya@intel.com,
	nandhini.srikandan@intel.com, rashmi.a@intel.com
Subject: [PATCH v2 2/4] dt-bindings: mmc: Add bindings for Intel Thunder Bay SoC
Date: Sun, 29 Aug 2021 23:54:41 +0530	[thread overview]
Message-ID: <20210829182443.30802-3-rashmi.a@intel.com> (raw)
In-Reply-To: <20210829182443.30802-1-rashmi.a@intel.com>

From: Rashmi A <rashmi.a@intel.com>

Add documentation for Arasan SDHCI controller in Thunder Bay SOC.

Signed-off-by: Rashmi A <rashmi.a@intel.com>
---
 .../devicetree/bindings/mmc/arasan,sdhci.yaml | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
index 37a5fe7b26dc..23abb7e8b9d8 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
@@ -88,6 +88,12 @@ properties:
         description:
           For this device it is strongly suggested to include
           arasan,soc-ctl-syscon.
+      - items:
+          - const: intel,thunderbay-sdhci-5.1   # Intel Thunder Bay eMMC PHY
+          - const: arasan,sdhci-5.1
+        description:
+          For this device it is strongly suggested to include
+          clock-output-names and '#clock-cells'.
 
   reg:
     maxItems: 1
@@ -301,3 +307,22 @@ examples:
                    <&scmi_clk KEEM_BAY_PSS_SD0>;
           arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
     };
+
+  - |
+    #define EMMC_XIN_CLK
+    #define EMMC_AXI_CLK
+    #define TBH_PSS_EMMC_RST_N
+    mmc@80420000 {
+          compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
+          interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
+          reg = <0x80420000 0x400>;
+          clocks = <&scmi_clk EMMC_XIN_CLK>,
+                   <&scmi_clk EMMC_AXI_CLK>;
+          clock-names = "clk_xin", "clk_ahb";
+          phys = <&emmc_phy>;
+          phy-names = "phy_arasan";
+          assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
+          clock-output-names = "emmc_cardclock";
+          resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
+          #clock-cells = <0x0>;
+    };
-- 
2.17.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: rashmi.a@intel.com
To: michal.simek@xilinx.com, ulf.hansson@linaro.org,
	linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kishon@ti.com, vkoul@kernel.org,
	andriy.shevchenko@linux.intel.com, linux-phy@lists.infradead.org
Cc: mgross@linux.intel.com, kris.pan@linux.intel.com,
	furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com,
	adrian.hunter@intel.com, mahesh.r.vaidya@intel.com,
	nandhini.srikandan@intel.com, rashmi.a@intel.com
Subject: [PATCH v2 2/4] dt-bindings: mmc: Add bindings for Intel Thunder Bay SoC
Date: Sun, 29 Aug 2021 23:54:41 +0530	[thread overview]
Message-ID: <20210829182443.30802-3-rashmi.a@intel.com> (raw)
In-Reply-To: <20210829182443.30802-1-rashmi.a@intel.com>

From: Rashmi A <rashmi.a@intel.com>

Add documentation for Arasan SDHCI controller in Thunder Bay SOC.

Signed-off-by: Rashmi A <rashmi.a@intel.com>
---
 .../devicetree/bindings/mmc/arasan,sdhci.yaml | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
index 37a5fe7b26dc..23abb7e8b9d8 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
@@ -88,6 +88,12 @@ properties:
         description:
           For this device it is strongly suggested to include
           arasan,soc-ctl-syscon.
+      - items:
+          - const: intel,thunderbay-sdhci-5.1   # Intel Thunder Bay eMMC PHY
+          - const: arasan,sdhci-5.1
+        description:
+          For this device it is strongly suggested to include
+          clock-output-names and '#clock-cells'.
 
   reg:
     maxItems: 1
@@ -301,3 +307,22 @@ examples:
                    <&scmi_clk KEEM_BAY_PSS_SD0>;
           arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
     };
+
+  - |
+    #define EMMC_XIN_CLK
+    #define EMMC_AXI_CLK
+    #define TBH_PSS_EMMC_RST_N
+    mmc@80420000 {
+          compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
+          interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
+          reg = <0x80420000 0x400>;
+          clocks = <&scmi_clk EMMC_XIN_CLK>,
+                   <&scmi_clk EMMC_AXI_CLK>;
+          clock-names = "clk_xin", "clk_ahb";
+          phys = <&emmc_phy>;
+          phy-names = "phy_arasan";
+          assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
+          clock-output-names = "emmc_cardclock";
+          resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
+          #clock-cells = <0x0>;
+    };
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-08-29 18:25 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-29 18:24 [PATCH v2 0/4] Add support of eMMC PHY for Intel Thunder Bay rashmi.a
2021-08-29 18:24 ` rashmi.a
2021-08-29 18:24 ` rashmi.a
2021-08-29 18:24 ` [PATCH v2 1/4] mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver rashmi.a
2021-08-29 18:24   ` rashmi.a
2021-08-29 18:24   ` rashmi.a
2021-08-29 18:24 ` rashmi.a [this message]
2021-08-29 18:24   ` [PATCH v2 2/4] dt-bindings: mmc: Add bindings for Intel Thunder Bay SoC rashmi.a
2021-08-29 18:24   ` rashmi.a
2021-08-29 18:24 ` [PATCH v2 3/4] dt-bindings: phy: intel: Add Thunder Bay eMMC PHY bindings rashmi.a
2021-08-29 18:24   ` rashmi.a
2021-08-29 18:24   ` rashmi.a
2021-08-29 18:24 ` [PATCH v2 4/4] phy: intel: Add Thunder Bay eMMC PHY support rashmi.a
2021-08-29 18:24   ` rashmi.a
2021-08-29 18:24   ` rashmi.a
2021-09-14 11:23 ` [PATCH v2 0/4] Add support of eMMC PHY for Intel Thunder Bay Ulf Hansson
2021-09-14 11:23   ` Ulf Hansson
2021-09-14 11:23   ` Ulf Hansson
2021-10-04  6:04   ` A, Rashmi
2021-10-04  6:04     ` A, Rashmi
2021-10-04  6:04     ` A, Rashmi
2021-10-05 10:35     ` Vinod Koul
2021-10-05 10:35       ` Vinod Koul
2021-10-05 10:35       ` Vinod Koul
2021-10-25  5:46       ` A, Rashmi
2021-10-25  5:46         ` A, Rashmi
2021-10-25  5:46         ` A, Rashmi
2021-10-25  7:03         ` Vinod Koul
2021-10-25  7:03           ` Vinod Koul
2021-10-25  7:03           ` Vinod Koul

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