From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> To: intel-gfx@lists.freedesktop.org, Lionel G Landwerlin <lionel.g.landwerlin@intel.com>, Ashutosh Dixit <ashutosh.dixit@intel.com> Cc: dri-devel@lists.freedesktop.org, daniel.vetter@ffwll.ch, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, jason@jlekstrand.net Subject: [PATCH 3/8] drm/i915/gt: Check for conflicting RING_NONPRIV Date: Mon, 30 Aug 2021 12:38:46 -0700 [thread overview] Message-ID: <20210830193851.15607-4-umesh.nerlige.ramappa@intel.com> (raw) In-Reply-To: <20210830193851.15607-1-umesh.nerlige.ramappa@intel.com> From: Chris Wilson <chris@chris-wilson.co.uk> Strip the encoded bits from the register offset so that we only use the address for looking up the RING_NONPRIV entry. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++++++-------- 1 file changed, 42 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6928f250cafe..df452a718200 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -80,18 +80,44 @@ static void wa_init_finish(struct i915_wa_list *wal) wal->wa_count, wal->name, wal->engine_name); } +static u32 reg_offset(i915_reg_t reg) +{ + return i915_mmio_reg_offset(reg) & RING_FORCE_TO_NONPRIV_ADDRESS_MASK; +} + +static u32 reg_flags(i915_reg_t reg) +{ + return i915_mmio_reg_offset(reg) & ~RING_FORCE_TO_NONPRIV_ADDRESS_MASK; +} + +__maybe_unused +static bool is_nonpriv_flags_valid(u32 flags) +{ + /* Check only valid flag bits are set */ + if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) + return false; + + /* NB: Only 3 out of 4 enum values are valid for access field */ + if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == + RING_FORCE_TO_NONPRIV_ACCESS_INVALID) + return false; + + return true; +} + static int wa_index(struct i915_wa_list *wal, i915_reg_t reg) { - unsigned int addr = i915_mmio_reg_offset(reg); int start = 0, end = wal->count; + u32 addr = reg_offset(reg); /* addr and wal->list[].reg, both include the R/W flags */ while (start < end) { unsigned int mid = start + (end - start) / 2; + u32 pos = reg_offset(wal->list[mid].reg); - if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) + if (pos < addr) start = mid + 1; - else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) + else if (pos > addr) end = mid; else return mid; @@ -117,13 +143,22 @@ static void __wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) struct i915_wa *wa_; int index; + GEM_BUG_ON(!is_nonpriv_flags_valid(reg_flags(wa->reg))); + index = wa_index(wal, wa->reg); if (index >= 0) { wa_ = &wal->list[index]; + if (i915_mmio_reg_offset(wa->reg) != + i915_mmio_reg_offset(wa_->reg)) { + DRM_ERROR("Discarding incompatible w/a for reg %04x\n", + reg_offset(wa->reg)); + return; + } + if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", - i915_mmio_reg_offset(wa_->reg), + reg_offset(wa_->reg), wa_->clr, wa_->set); wa_->set &= ~wa->clr; @@ -141,10 +176,8 @@ static void __wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) *wa_ = *wa; while (wa_-- > wal->list) { - GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == - i915_mmio_reg_offset(wa_[1].reg)); - if (i915_mmio_reg_offset(wa_[1].reg) > - i915_mmio_reg_offset(wa_[0].reg)) + GEM_BUG_ON(reg_offset(wa_[0].reg) == reg_offset(wa_[1].reg)); + if (reg_offset(wa_[1].reg) > reg_offset(wa_[0].reg)) break; swap(wa_[1], wa_[0]); @@ -160,7 +193,7 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) if (IS_ALIGNED(wal->count, grow) && /* Either uninitialized or full. */ wa_list_grow(wal, ALIGN(wal->count + 1, grow), GFP_KERNEL)) { DRM_ERROR("Unable to store w/a for reg %04x\n", - i915_mmio_reg_offset(wa->reg)); + reg_offset(wa->reg)); return; } @@ -1367,21 +1400,6 @@ bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) return wa_list_verify(gt, >->i915->gt_wa_list, from); } -__maybe_unused -static bool is_nonpriv_flags_valid(u32 flags) -{ - /* Check only valid flag bits are set */ - if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) - return false; - - /* NB: Only 3 out of 4 enum values are valid for access field */ - if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == - RING_FORCE_TO_NONPRIV_ACCESS_INVALID) - return false; - - return true; -} - static void whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) { -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> To: intel-gfx@lists.freedesktop.org, Lionel G Landwerlin <lionel.g.landwerlin@intel.com>, Ashutosh Dixit <ashutosh.dixit@intel.com> Cc: dri-devel@lists.freedesktop.org, daniel.vetter@ffwll.ch, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, jason@jlekstrand.net Subject: [Intel-gfx] [PATCH 3/8] drm/i915/gt: Check for conflicting RING_NONPRIV Date: Mon, 30 Aug 2021 12:38:46 -0700 [thread overview] Message-ID: <20210830193851.15607-4-umesh.nerlige.ramappa@intel.com> (raw) In-Reply-To: <20210830193851.15607-1-umesh.nerlige.ramappa@intel.com> From: Chris Wilson <chris@chris-wilson.co.uk> Strip the encoded bits from the register offset so that we only use the address for looking up the RING_NONPRIV entry. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++++++-------- 1 file changed, 42 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6928f250cafe..df452a718200 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -80,18 +80,44 @@ static void wa_init_finish(struct i915_wa_list *wal) wal->wa_count, wal->name, wal->engine_name); } +static u32 reg_offset(i915_reg_t reg) +{ + return i915_mmio_reg_offset(reg) & RING_FORCE_TO_NONPRIV_ADDRESS_MASK; +} + +static u32 reg_flags(i915_reg_t reg) +{ + return i915_mmio_reg_offset(reg) & ~RING_FORCE_TO_NONPRIV_ADDRESS_MASK; +} + +__maybe_unused +static bool is_nonpriv_flags_valid(u32 flags) +{ + /* Check only valid flag bits are set */ + if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) + return false; + + /* NB: Only 3 out of 4 enum values are valid for access field */ + if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == + RING_FORCE_TO_NONPRIV_ACCESS_INVALID) + return false; + + return true; +} + static int wa_index(struct i915_wa_list *wal, i915_reg_t reg) { - unsigned int addr = i915_mmio_reg_offset(reg); int start = 0, end = wal->count; + u32 addr = reg_offset(reg); /* addr and wal->list[].reg, both include the R/W flags */ while (start < end) { unsigned int mid = start + (end - start) / 2; + u32 pos = reg_offset(wal->list[mid].reg); - if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) + if (pos < addr) start = mid + 1; - else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) + else if (pos > addr) end = mid; else return mid; @@ -117,13 +143,22 @@ static void __wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) struct i915_wa *wa_; int index; + GEM_BUG_ON(!is_nonpriv_flags_valid(reg_flags(wa->reg))); + index = wa_index(wal, wa->reg); if (index >= 0) { wa_ = &wal->list[index]; + if (i915_mmio_reg_offset(wa->reg) != + i915_mmio_reg_offset(wa_->reg)) { + DRM_ERROR("Discarding incompatible w/a for reg %04x\n", + reg_offset(wa->reg)); + return; + } + if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", - i915_mmio_reg_offset(wa_->reg), + reg_offset(wa_->reg), wa_->clr, wa_->set); wa_->set &= ~wa->clr; @@ -141,10 +176,8 @@ static void __wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) *wa_ = *wa; while (wa_-- > wal->list) { - GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == - i915_mmio_reg_offset(wa_[1].reg)); - if (i915_mmio_reg_offset(wa_[1].reg) > - i915_mmio_reg_offset(wa_[0].reg)) + GEM_BUG_ON(reg_offset(wa_[0].reg) == reg_offset(wa_[1].reg)); + if (reg_offset(wa_[1].reg) > reg_offset(wa_[0].reg)) break; swap(wa_[1], wa_[0]); @@ -160,7 +193,7 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) if (IS_ALIGNED(wal->count, grow) && /* Either uninitialized or full. */ wa_list_grow(wal, ALIGN(wal->count + 1, grow), GFP_KERNEL)) { DRM_ERROR("Unable to store w/a for reg %04x\n", - i915_mmio_reg_offset(wa->reg)); + reg_offset(wa->reg)); return; } @@ -1367,21 +1400,6 @@ bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) return wa_list_verify(gt, >->i915->gt_wa_list, from); } -__maybe_unused -static bool is_nonpriv_flags_valid(u32 flags) -{ - /* Check only valid flag bits are set */ - if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) - return false; - - /* NB: Only 3 out of 4 enum values are valid for access field */ - if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == - RING_FORCE_TO_NONPRIV_ACCESS_INVALID) - return false; - - return true; -} - static void whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) { -- 2.20.1
next prev parent reply other threads:[~2021-08-30 19:39 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-30 19:38 [PATCH 0/8] Enable triggered perf query for Xe_HP Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` [PATCH 1/8] drm/i915/gt: Lock intel_engine_apply_whitelist with uncore->lock Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` [PATCH 2/8] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` Umesh Nerlige Ramappa [this message] 2021-08-30 19:38 ` [Intel-gfx] [PATCH 3/8] drm/i915/gt: Check for conflicting RING_NONPRIV Umesh Nerlige Ramappa 2021-08-31 3:39 ` kernel test robot 2021-08-31 3:39 ` kernel test robot 2021-08-30 19:38 ` [PATCH 4/8] drm/i915/gt: Enable dynamic adjustment of RING_NONPRIV Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] [PATCH 5/8] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa 2021-08-30 19:38 ` Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] [PATCH 6/8] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa 2021-08-30 19:38 ` Umesh Nerlige Ramappa 2021-08-30 19:38 ` [PATCH 7/8] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] [PATCH 8/8] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa 2021-08-30 19:38 ` Umesh Nerlige Ramappa 2021-08-31 12:55 ` Daniel Vetter 2021-08-31 12:55 ` [Intel-gfx] " Daniel Vetter 2021-08-31 20:35 ` Umesh Nerlige Ramappa 2021-08-31 20:35 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 22:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable triggered perf query for Xe_HP (rev2) Patchwork -- strict thread matches above, loose matches on Subject: below -- 2021-08-03 20:13 [PATCH 0/8] Enable triggered perf query for Xe_HP Umesh Nerlige Ramappa 2021-08-03 20:13 ` [PATCH 3/8] drm/i915/gt: Check for conflicting RING_NONPRIV Umesh Nerlige Ramappa
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210830193851.15607-4-umesh.nerlige.ramappa@intel.com \ --to=umesh.nerlige.ramappa@intel.com \ --cc=ashutosh.dixit@intel.com \ --cc=daniel.vetter@ffwll.ch \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=jason@jlekstrand.net \ --cc=joonas.lahtinen@linux.intel.com \ --cc=lionel.g.landwerlin@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.