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From: John.C.Harrison@Intel.com
To: Intel-GFX@Lists.FreeDesktop.Org
Cc: DRI-Devel@Lists.FreeDesktop.Org, Matthew Brost <matthew.brost@intel.com>
Subject: [PATCH 4/7] drm/i915/guc: Enable GuC submission by default on DG1
Date: Tue, 31 Aug 2021 19:20:40 -0700	[thread overview]
Message-ID: <20210901022043.2395135-5-John.C.Harrison@Intel.com> (raw)
In-Reply-To: <20210901022043.2395135-1-John.C.Harrison@Intel.com>

From: Matthew Brost <matthew.brost@intel.com>

Enable GuC submission by default on DG1

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b104fb7607eb..d94ff12fdb95 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -35,7 +35,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
 	}
 
 	/* Intermediate platforms are HuC authentication only */
-	if (IS_DG1(i915) || IS_ALDERLAKE_S(i915)) {
+	if (IS_ALDERLAKE_S(i915)) {
 		i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
 		return;
 	}
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: John.C.Harrison@Intel.com
To: Intel-GFX@Lists.FreeDesktop.Org
Cc: DRI-Devel@Lists.FreeDesktop.Org, Matthew Brost <matthew.brost@intel.com>
Subject: [Intel-gfx] [PATCH 4/7] drm/i915/guc: Enable GuC submission by default on DG1
Date: Tue, 31 Aug 2021 19:20:40 -0700	[thread overview]
Message-ID: <20210901022043.2395135-5-John.C.Harrison@Intel.com> (raw)
In-Reply-To: <20210901022043.2395135-1-John.C.Harrison@Intel.com>

From: Matthew Brost <matthew.brost@intel.com>

Enable GuC submission by default on DG1

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b104fb7607eb..d94ff12fdb95 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -35,7 +35,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
 	}
 
 	/* Intermediate platforms are HuC authentication only */
-	if (IS_DG1(i915) || IS_ALDERLAKE_S(i915)) {
+	if (IS_ALDERLAKE_S(i915)) {
 		i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
 		return;
 	}
-- 
2.25.1


  parent reply	other threads:[~2021-09-01  2:21 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-01  2:20 [PATCH 0/7] [CI] Enable GuC submission by default on DG1 John.C.Harrison
2021-09-01  2:20 ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 1/7] drm/i915: Do not define vma on stack John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 2/7] drm/i915/guc: put all guc objects in lmem when available John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01 16:12   ` Matthew Auld
2021-09-01  2:20 ` [PATCH 3/7] drm/i915/guc: Add DG1 GuC / HuC firmware defs John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` John.C.Harrison [this message]
2021-09-01  2:20   ` [Intel-gfx] [PATCH 4/7] drm/i915/guc: Enable GuC submission by default on DG1 John.C.Harrison
2021-09-01  2:20 ` [PATCH 5/7] Me: Allow relocs on DG1 for CI John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 6/7] Me: Workaround LMEM blow up John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:20 ` [PATCH 7/7] Me: Dump GuC log to dmesg on SLPC load failure John.C.Harrison
2021-09-01  2:20   ` [Intel-gfx] " John.C.Harrison
2021-09-01  2:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC submission by default on DG1 (rev2) Patchwork
2021-09-01  3:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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