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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: harry.wentland@amd.com, ville.syrjala@linux.intel.com,
	ppaalanen@gmail.com, brian.starkey@arm.com,
	sebastian@sebastianwick.net, Shashank.Sharma@amd.com,
	Uma Shankar <uma.shankar@intel.com>
Subject: [Intel-gfx] [RFC v2 06/22] drm/i915/xelpd: Add register definitions for Plane Degamma
Date: Tue,  7 Sep 2021 03:08:48 +0530	[thread overview]
Message-ID: <20210906213904.27918-7-uma.shankar@intel.com> (raw)
In-Reply-To: <20210906213904.27918-1-uma.shankar@intel.com>

Add macros to define Plane Degamma registers

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 313432ed6196..919982c878ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -262,6 +262,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
 					      DISPLAY_MMIO_BASE(dev_priv))
 
+/* Plane Gamma Registers */
+#define _MMIO_PLANE_GAMC(plane, i, a, b)  _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
 #define _MASKED_FIELD(mask, value) ({					   \
 	if (__builtin_constant_p(mask))					   \
@@ -11366,6 +11369,55 @@ enum skl_power_gate {
 					_PAL_PREC_MULTI_SEG_DATA_A, \
 					_PAL_PREC_MULTI_SEG_DATA_B)
 
+/* Display13 Plane Degmma Reg */
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A	0x701d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B	0x711d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A	0x702d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B	0x712d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
+						_PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
+						_PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i)	\
+		_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
+		_PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A	0x701d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B	0x711d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A	0x702d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B	0x712d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
+						_PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
+						_PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)	\
+		_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
+		_PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_A	0x704d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_B	0x714d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_A	0x705d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_B	0x715d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \
+						_PLANE_PRE_CSC_GAMC_INDEX_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \
+						_PLANE_PRE_CSC_GAMC_INDEX_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i)	\
+		_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
+		_PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_1_A	0x704d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1_B	0x714d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_A	0x705d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_B	0x715d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \
+						_PLANE_PRE_CSC_GAMC_DATA_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \
+						_PLANE_PRE_CSC_GAMC_DATA_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)	\
+		_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
+		_PLANE_PRE_CSC_GAMC_DATA_2(pipe))
+
 /* pipe CSC & degamma/gamma LUTs on CHV */
 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
-- 
2.26.2


WARNING: multiple messages have this Message-ID (diff)
From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: harry.wentland@amd.com, ville.syrjala@linux.intel.com,
	ppaalanen@gmail.com, brian.starkey@arm.com,
	sebastian@sebastianwick.net, Shashank.Sharma@amd.com,
	Uma Shankar <uma.shankar@intel.com>
Subject: [RFC v2 06/22] drm/i915/xelpd: Add register definitions for Plane Degamma
Date: Tue,  7 Sep 2021 03:08:48 +0530	[thread overview]
Message-ID: <20210906213904.27918-7-uma.shankar@intel.com> (raw)
In-Reply-To: <20210906213904.27918-1-uma.shankar@intel.com>

Add macros to define Plane Degamma registers

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 313432ed6196..919982c878ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -262,6 +262,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
 					      DISPLAY_MMIO_BASE(dev_priv))
 
+/* Plane Gamma Registers */
+#define _MMIO_PLANE_GAMC(plane, i, a, b)  _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
 #define _MASKED_FIELD(mask, value) ({					   \
 	if (__builtin_constant_p(mask))					   \
@@ -11366,6 +11369,55 @@ enum skl_power_gate {
 					_PAL_PREC_MULTI_SEG_DATA_A, \
 					_PAL_PREC_MULTI_SEG_DATA_B)
 
+/* Display13 Plane Degmma Reg */
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A	0x701d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B	0x711d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A	0x702d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B	0x712d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
+						_PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
+						_PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i)	\
+		_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
+		_PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A	0x701d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B	0x711d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A	0x702d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B	0x712d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
+						_PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
+						_PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)	\
+		_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
+		_PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_A	0x704d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_B	0x714d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_A	0x705d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_B	0x715d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \
+						_PLANE_PRE_CSC_GAMC_INDEX_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \
+						_PLANE_PRE_CSC_GAMC_INDEX_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i)	\
+		_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
+		_PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_1_A	0x704d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1_B	0x714d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_A	0x705d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_B	0x715d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \
+						_PLANE_PRE_CSC_GAMC_DATA_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \
+						_PLANE_PRE_CSC_GAMC_DATA_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)	\
+		_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
+		_PLANE_PRE_CSC_GAMC_DATA_2(pipe))
+
 /* pipe CSC & degamma/gamma LUTs on CHV */
 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
-- 
2.26.2


  parent reply	other threads:[~2021-09-06 21:01 UTC|newest]

Thread overview: 154+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-06 21:38 [Intel-gfx] [RFC v2 00/22] Add Support for Plane Color Lut and CSC features Uma Shankar
2021-09-06 21:38 ` Uma Shankar
2021-09-06 21:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Support for Plane Color Lut and CSC features (rev2) Patchwork
2021-09-06 21:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-10-12 10:30   ` Pekka Paalanen
2021-10-12 10:30     ` [Intel-gfx] " Pekka Paalanen
2021-10-12 10:35     ` Simon Ser
2021-10-12 10:35       ` [Intel-gfx] " Simon Ser
2021-10-12 12:00       ` Pekka Paalanen
2021-10-12 12:00         ` [Intel-gfx] " Pekka Paalanen
2021-10-12 19:11         ` Shankar, Uma
2021-10-12 19:11           ` [Intel-gfx] " Shankar, Uma
2021-10-13  7:25           ` Pekka Paalanen
2021-10-13  7:25             ` [Intel-gfx] " Pekka Paalanen
2021-10-14 19:46             ` Shankar, Uma
2021-10-14 19:46               ` [Intel-gfx] " Shankar, Uma
2021-10-12 20:58     ` Shankar, Uma
2021-10-12 20:58       ` [Intel-gfx] " Shankar, Uma
2021-10-13  8:30       ` Pekka Paalanen
2021-10-13  8:30         ` [Intel-gfx] " Pekka Paalanen
2021-10-14 19:44         ` Shankar, Uma
2021-10-14 19:44           ` [Intel-gfx] " Shankar, Uma
2021-10-15  7:42           ` Pekka Paalanen
2021-10-15  7:42             ` [Intel-gfx] " Pekka Paalanen
2021-10-26 15:11             ` Harry Wentland
2021-10-26 15:11               ` [Intel-gfx] " Harry Wentland
2021-10-26 15:36           ` Harry Wentland
2021-10-26 15:36             ` [Intel-gfx] " Harry Wentland
2021-10-27  8:00             ` Pekka Paalanen
2021-10-27  8:00               ` [Intel-gfx] " Pekka Paalanen
2021-10-27 12:48               ` Harry Wentland
2021-10-27 12:48                 ` Harry Wentland
2021-10-26 15:40       ` Harry Wentland
2021-10-26 15:40         ` [Intel-gfx] " Harry Wentland
2021-11-23 15:05   ` Harry Wentland
2021-11-23 15:05     ` [Intel-gfx] " Harry Wentland
2021-11-25 20:43     ` Shankar, Uma
2021-11-25 20:43       ` [Intel-gfx] " Shankar, Uma
2021-11-26  8:21       ` Pekka Paalanen
2021-11-26  8:21         ` [Intel-gfx] " Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 02/22] drm: Add Enhanced Gamma and color lut range attributes Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-11-03 15:08   ` Harry Wentland
2021-11-03 15:08     ` [Intel-gfx] " Harry Wentland
2021-11-04  8:38     ` Pekka Paalanen
2021-11-04  8:38       ` [Intel-gfx] " Pekka Paalanen
2021-11-04 16:27       ` Harry Wentland
2021-11-04 16:27         ` [Intel-gfx] " Harry Wentland
2021-11-05 11:49         ` Ville Syrjälä
2021-11-05 11:49           ` [Intel-gfx] " Ville Syrjälä
2021-11-09 20:22           ` Harry Wentland
2021-11-09 20:22             ` [Intel-gfx] " Harry Wentland
2021-11-08  9:54         ` Pekka Paalanen
2021-11-08  9:54           ` [Intel-gfx] " Pekka Paalanen
2021-11-09 20:47           ` Harry Wentland
2021-11-09 20:47             ` [Intel-gfx] " Harry Wentland
2021-11-09 22:02             ` Ville Syrjälä
2021-11-09 22:02               ` [Intel-gfx] " Ville Syrjälä
2021-11-10  8:49               ` Pekka Paalanen
2021-11-10  8:49                 ` [Intel-gfx] " Pekka Paalanen
2021-11-10 11:55                 ` Ville Syrjälä
2021-11-10 11:55                   ` [Intel-gfx] " Ville Syrjälä
2021-11-10 15:17                   ` Harry Wentland
2021-11-10 15:17                     ` [Intel-gfx] " Harry Wentland
2021-11-11  8:22                     ` Pekka Paalanen
2021-11-11  8:22                       ` [Intel-gfx] " Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 03/22] drm: Add Plane Degamma Mode property Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-10-12 11:50   ` Pekka Paalanen
2021-10-12 11:50     ` [Intel-gfx] " Pekka Paalanen
2021-10-12 21:02     ` Shankar, Uma
2021-10-12 21:02       ` [Intel-gfx] " Shankar, Uma
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 04/22] drm: Add Plane Degamma Lut property Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-11-03 15:10   ` Harry Wentland
2021-11-03 15:10     ` [Intel-gfx] " Harry Wentland
2021-11-05 12:59     ` Ville Syrjälä
2021-11-05 12:59       ` [Intel-gfx] " Ville Syrjälä
2021-11-09 20:19       ` Harry Wentland
2021-11-09 20:19         ` [Intel-gfx] " Harry Wentland
2021-11-09 21:45         ` Ville Syrjälä
2021-11-09 21:45           ` [Intel-gfx] " Ville Syrjälä
2021-11-09 21:56           ` Harry Wentland
2021-11-09 21:56             ` [Intel-gfx] " Harry Wentland
2021-11-11 15:17   ` Harry Wentland
2021-11-11 15:17     ` [Intel-gfx] " Harry Wentland
2021-11-11 16:42     ` Ville Syrjälä
2021-11-11 16:42       ` [Intel-gfx] " Ville Syrjälä
2021-11-11 20:42       ` Shankar, Uma
2021-11-11 20:42         ` [Intel-gfx] " Shankar, Uma
2021-11-11 21:10         ` Harry Wentland
2021-11-11 21:10           ` [Intel-gfx] " Harry Wentland
2021-11-11 21:58           ` Shankar, Uma
2021-11-11 21:58             ` [Intel-gfx] " Shankar, Uma
2021-11-12  8:37             ` Pekka Paalanen
2021-11-12  8:37               ` [Intel-gfx] " Pekka Paalanen
2021-11-23 14:40               ` Harry Wentland
2021-11-23 14:40                 ` [Intel-gfx] " Harry Wentland
2021-11-12 14:54           ` Ville Syrjälä
2021-11-12 14:54             ` [Intel-gfx] " Ville Syrjälä
2021-11-16  8:15             ` Pekka Paalanen
2021-11-16  8:15               ` [Intel-gfx] " Pekka Paalanen
2021-09-06 21:38 ` Uma Shankar [this message]
2021-09-06 21:38   ` [RFC v2 06/22] drm/i915/xelpd: Add register definitions for Plane Degamma Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 07/22] drm/i915/xelpd: Enable plane color features Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 08/22] drm/i915/xelpd: Add color capabilities of SDR planes Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 09/22] drm/i915/xelpd: Program Plane Degamma Registers Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 10/22] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 11/22] drm/i915/xelpd: Initialize plane color features Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [RFC v2 12/22] drm/i915/xelpd: Load plane color luts from atomic flip Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 13/22] drm: Add Plane CTM property Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 14/22] drm: Add helper to attach Plane ctm property Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 15/22] drm/i915/xelpd: Define Plane CSC Registers Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 16/22] drm/i915/xelpd: Enable Plane CSC Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 17/22] drm: Add Plane Gamma Mode property Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 18/22] drm: Add Plane Gamma Lut property Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 19/22] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 20/22] drm/i915/xelpd: Add register definitions for Plane Gamma Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 21/22] drm/i915/xelpd: Program Plane Gamma Registers Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 22/22] drm/i915/xelpd: Enable plane gamma Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Add Support for Plane Color Lut and CSC features (rev2) Patchwork
2021-09-06 23:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-12 11:55 ` [RFC v2 00/22] Add Support for Plane Color Lut and CSC features Pekka Paalanen
2021-10-12 11:55   ` [Intel-gfx] " Pekka Paalanen
2021-10-12 21:01   ` Shankar, Uma
2021-10-12 21:01     ` [Intel-gfx] " Shankar, Uma
2021-10-26 15:02     ` Harry Wentland
2021-10-26 15:02       ` [Intel-gfx] " Harry Wentland
2021-10-27  8:18       ` Pekka Paalanen
2021-10-27  8:18         ` [Intel-gfx] " Pekka Paalanen
2022-02-02 16:11 ` Harry Wentland
2022-02-02 16:11   ` [Intel-gfx] " Harry Wentland
2022-02-03 17:22   ` Shankar, Uma
2022-02-03 17:22     ` [Intel-gfx] " Shankar, Uma

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