From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <john.c.harrison@intel.com> Subject: [PATCH 4/5] drm/i915/guc: Enable GuC submission by default on DG1 Date: Mon, 13 Sep 2021 21:49:32 -0700 [thread overview] Message-ID: <20210914044933.22932-5-matthew.brost@intel.com> (raw) In-Reply-To: <20210914044933.22932-1-matthew.brost@intel.com> Enable GuC submission by default on DG1 Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 86c318516e14..2fef3b0bbe95 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -35,7 +35,7 @@ static void uc_expand_default_options(struct intel_uc *uc) } /* Intermediate platforms are HuC authentication only */ - if (IS_DG1(i915) || IS_ALDERLAKE_S(i915)) { + if (IS_ALDERLAKE_S(i915)) { i915->params.enable_guc = ENABLE_GUC_LOAD_HUC; return; } -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <john.c.harrison@intel.com> Subject: [Intel-gfx] [PATCH 4/5] drm/i915/guc: Enable GuC submission by default on DG1 Date: Mon, 13 Sep 2021 21:49:32 -0700 [thread overview] Message-ID: <20210914044933.22932-5-matthew.brost@intel.com> (raw) In-Reply-To: <20210914044933.22932-1-matthew.brost@intel.com> Enable GuC submission by default on DG1 Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 86c318516e14..2fef3b0bbe95 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -35,7 +35,7 @@ static void uc_expand_default_options(struct intel_uc *uc) } /* Intermediate platforms are HuC authentication only */ - if (IS_DG1(i915) || IS_ALDERLAKE_S(i915)) { + if (IS_ALDERLAKE_S(i915)) { i915->params.enable_guc = ENABLE_GUC_LOAD_HUC; return; } -- 2.32.0
next prev parent reply other threads:[~2021-09-14 4:55 UTC|newest] Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-14 4:49 [PATCH 0/5] Enable GuC submission by default on DG1 Matthew Brost 2021-09-14 4:49 ` [Intel-gfx] " Matthew Brost 2021-09-14 4:49 ` [PATCH 1/5] drm/i915: Do not define vma on stack Matthew Brost 2021-09-14 4:49 ` [Intel-gfx] " Matthew Brost 2021-09-14 5:04 ` Dave Airlie 2021-09-14 5:04 ` [Intel-gfx] " Dave Airlie 2021-09-14 15:36 ` Matthew Brost 2021-09-14 15:36 ` [Intel-gfx] " Matthew Brost 2021-09-14 20:05 ` Daniel Vetter 2021-09-14 21:10 ` Matthew Brost 2021-09-17 12:31 ` Daniel Vetter 2021-09-14 4:49 ` [PATCH 2/5] drm/i915/guc: put all guc objects in lmem when available Matthew Brost 2021-09-14 4:49 ` [Intel-gfx] " Matthew Brost 2021-09-14 4:49 ` [PATCH 3/5] drm/i915/guc: Add DG1 GuC / HuC firmware defs Matthew Brost 2021-09-14 4:49 ` [Intel-gfx] " Matthew Brost 2021-09-14 4:49 ` Matthew Brost [this message] 2021-09-14 4:49 ` [Intel-gfx] [PATCH 4/5] drm/i915/guc: Enable GuC submission by default on DG1 Matthew Brost 2021-09-14 4:49 ` [PATCH 5/5] drm/i915/guc: Use i915_gem_object_is_lmem in i915_gem_object_is_lmem Matthew Brost 2021-09-14 4:49 ` [Intel-gfx] " Matthew Brost 2021-09-14 5:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable GuC submission by default on DG1 (rev5) Patchwork 2021-09-14 6:01 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2021-09-14 16:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable GuC submission by default on DG1 (rev6) Patchwork 2021-09-14 16:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2021-09-16 16:28 [PATCH 0/5] Enable GuC submission by default on DG1 Matthew Brost 2021-09-16 16:28 ` [PATCH 4/5] drm/i915/guc: " Matthew Brost 2021-09-16 17:23 ` John Harrison
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