[PATCH v3 04/10] coresight: trbe: Ensure the format flag is set always

From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org,
	anshuman.khandual@arm.com, mike.leach@linaro.org,
	leo.yan@linaro.org, tamas.zsoldos@arm.com,
	jinlmao@qti.qualcomm.com, al.grant@arm.com, denik@google.com,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v3 04/10] coresight: trbe: Ensure the format flag is set always
Date: Tue, 14 Sep 2021 11:26:35 +0100	[thread overview]
Message-ID: <20210914102641.1852544-5-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210914102641.1852544-1-suzuki.poulose@arm.com>

When the TRBE is stopped on truncating an event, we may not
set the FORMAT flag, even though the size of the record is 0.
Let us be consistent and not confuse the user.

To ensure that the format flag is always set on all the
records generated by TRBE, set the flag when we have a
new handle. Rather than deferring to the "end" operation,
which makes it clear. So, we can do this from

 -  arm_trbe_enable() -> When a new handle is provided by the
    CoreSight PMU, triggered via etm_event_start()
 -  trbe_handle_overflow() -> When we begin a new handle after
    closing the previous on overflow.

Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since v2:
  - Move the format flag setting to the beginning of a session
    than the ending (which can happen via various different paths)
---
 drivers/hwtracing/coresight/coresight-trbe.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index 176868496879..81bf183a73a1 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -554,8 +554,6 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
 	if (cpudata->mode != CS_MODE_PERF)
 		return 0;
 
-	perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
-
 	/*
 	 * We are about to disable the TRBE. And this could in turn
 	 * fill up the buffer triggering, an IRQ. This could be consumed
@@ -648,6 +646,7 @@ static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
 	if (mode != CS_MODE_PERF)
 		return -EINVAL;
 
+	perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
 	*this_cpu_ptr(drvdata->handle) = handle;
 	cpudata->buf = buf;
 	cpudata->mode = mode;
@@ -710,8 +709,7 @@ static void trbe_handle_overflow(struct perf_output_handle *handle)
 	 * Mark the buffer as truncated, as we have stopped the trace
 	 * collection upon the WRAP event, without stopping the source.
 	 */
-	perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW |
-				     PERF_AUX_FLAG_TRUNCATED);
+	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
 	perf_aux_output_end(handle, size);
 	event_data = perf_aux_output_begin(handle, event);
 	if (!event_data) {
@@ -725,6 +723,7 @@ static void trbe_handle_overflow(struct perf_output_handle *handle)
 		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
 		return;
 	}
+	perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
 	buf->trbe_limit = compute_trbe_buffer_limit(handle);
 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
 	if (buf->trbe_limit == buf->trbe_base) {
-- 
2.24.1


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