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From: Krish Sadhukhan <krish.sadhukhan@oracle.com>
To: kvm@vger.kernel.org
Cc: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com,
	vkuznets@redhat.com, wanpengli@tencent.com, joro@8bytes.org
Subject: [TEST PATCH 4/5] X86: Add #define for FLUSHBYASID CPUID bit
Date: Mon, 20 Sep 2021 19:51:33 -0400	[thread overview]
Message-ID: <20210920235134.101970-5-krish.sadhukhan@oracle.com> (raw)
In-Reply-To: <20210920235134.101970-1-krish.sadhukhan@oracle.com>

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
---
 lib/x86/processor.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/x86/processor.h b/lib/x86/processor.h
index f380321..9c716de 100644
--- a/lib/x86/processor.h
+++ b/lib/x86/processor.h
@@ -188,6 +188,7 @@ static inline bool is_intel(void)
 #define	X86_FEATURE_AMD_IBPB		(CPUID(0x80000008, 0, EBX, 12))
 #define	X86_FEATURE_NPT			(CPUID(0x8000000A, 0, EDX, 0))
 #define	X86_FEATURE_NRIPS		(CPUID(0x8000000A, 0, EDX, 3))
+#define	X86_FEATURE_FLUSHBYASID		(CPUID(0x8000000A, 0, EDX, 6))
 #define	X86_FEATURE_VGIF		(CPUID(0x8000000A, 0, EDX, 16))
 
 
-- 
2.27.0


  parent reply	other threads:[~2021-09-21  0:48 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-20 23:51 [PATCH 0/5] nSVM: Check for optional commands and reserved encodins of TLB_CONTROL in nested guests Krish Sadhukhan
2021-09-20 23:51 ` [PATCH 1/5] nSVM: Expose FLUSHBYASID CPUID feature to " Krish Sadhukhan
2021-09-24 10:58   ` Paolo Bonzini
2021-09-20 23:51 ` [PATCH 2/5] nSVM: Check for optional commands and reserved encodings of TLB_CONTROL in nested VMCB Krish Sadhukhan
2021-09-28 16:55   ` Paolo Bonzini
2023-09-06 15:59     ` Stefan Sterz
2023-09-06 20:40       ` Sean Christopherson
2021-09-20 23:51 ` [TEST PATCH 3/5] SVM: Add #defines for valid encodings of TLB_CONTROL VMCB field Krish Sadhukhan
2021-09-20 23:51 ` Krish Sadhukhan [this message]
2021-09-20 23:51 ` [TEST PATCH 5/5] nSVM: Test optional commands and reserved encodings of TLB_CONTROL in nested VMCB Krish Sadhukhan

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