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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Bin Meng <bmeng.cn@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends
Date: Tue, 21 Sep 2021 16:54:11 +1000	[thread overview]
Message-ID: <20210921065412.312381-21-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20210921065412.312381-1-alistair.francis@opensource.wdc.com>

From: Bin Meng <bmeng.cn@gmail.com>

The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
in fact it applies to M-mode and S-mode CSR too. Rename these macros
to have the COUNTEREN_ prefix.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210915084601.24304-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h |  8 ++++----
 target/riscv/csr.c      | 24 ++++++++++++------------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ce9dcc030c..999187a9ee 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -397,10 +397,10 @@
 #define HSTATUS32_WPRI       0xFF8FF87E
 #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
 
-#define HCOUNTEREN_CY        (1 << 0)
-#define HCOUNTEREN_TM        (1 << 1)
-#define HCOUNTEREN_IR        (1 << 2)
-#define HCOUNTEREN_HPM3      (1 << 3)
+#define COUNTEREN_CY         (1 << 0)
+#define COUNTEREN_TM         (1 << 1)
+#define COUNTEREN_IR         (1 << 2)
+#define COUNTEREN_HPM3       (1 << 3)
 
 /* Privilege modes */
 #define PRV_U 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ba9818f6a5..23fbbd3216 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -71,20 +71,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
     if (riscv_cpu_virt_enabled(env)) {
         switch (csrno) {
         case CSR_CYCLE:
-            if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
-                get_field(env->mcounteren, HCOUNTEREN_CY)) {
+            if (!get_field(env->hcounteren, COUNTEREN_CY) &&
+                get_field(env->mcounteren, COUNTEREN_CY)) {
                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
             }
             break;
         case CSR_TIME:
-            if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
-                get_field(env->mcounteren, HCOUNTEREN_TM)) {
+            if (!get_field(env->hcounteren, COUNTEREN_TM) &&
+                get_field(env->mcounteren, COUNTEREN_TM)) {
                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
             }
             break;
         case CSR_INSTRET:
-            if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
-                get_field(env->mcounteren, HCOUNTEREN_IR)) {
+            if (!get_field(env->hcounteren, COUNTEREN_IR) &&
+                get_field(env->mcounteren, COUNTEREN_IR)) {
                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
             }
             break;
@@ -98,20 +98,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
         if (riscv_cpu_is_32bit(env)) {
             switch (csrno) {
             case CSR_CYCLEH:
-                if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
-                    get_field(env->mcounteren, HCOUNTEREN_CY)) {
+                if (!get_field(env->hcounteren, COUNTEREN_CY) &&
+                    get_field(env->mcounteren, COUNTEREN_CY)) {
                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                 }
                 break;
             case CSR_TIMEH:
-                if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
-                    get_field(env->mcounteren, HCOUNTEREN_TM)) {
+                if (!get_field(env->hcounteren, COUNTEREN_TM) &&
+                    get_field(env->mcounteren, COUNTEREN_TM)) {
                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                 }
                 break;
             case CSR_INSTRETH:
-                if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
-                    get_field(env->mcounteren, HCOUNTEREN_IR)) {
+                if (!get_field(env->hcounteren, COUNTEREN_IR) &&
+                    get_field(env->mcounteren, COUNTEREN_IR)) {
                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                 }
                 break;
-- 
2.31.1



  parent reply	other threads:[~2021-09-21  7:10 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-21  6:53 [PULL v2 00/21] riscv-to-apply queue Alistair Francis
2021-09-21  6:53 ` [PULL v2 01/21] target/riscv: Update the ePMP CSR address Alistair Francis
2021-09-21  6:53 ` [PULL v2 02/21] target/riscv: Fix satp write Alistair Francis
2021-09-21  6:53 ` [PULL v2 03/21] target/riscv: Expose interrupt pending bits as GPIO lines Alistair Francis
2021-09-21  6:53 ` [PULL v2 04/21] hw/intc: sifive_clint: Use RISC-V CPU " Alistair Francis
2021-09-21  6:53 ` [PULL v2 05/21] hw/intc: ibex_plic: Convert the PLIC to use " Alistair Francis
2021-09-21  6:53 ` [PULL v2 06/21] hw/intc: sifive_plic: " Alistair Francis
2021-09-21  6:53 ` [PULL v2 07/21] hw/intc: ibex_timer: Convert the timer " Alistair Francis
2021-09-21  6:53 ` [PULL v2 08/21] hw/timer: Add SiFive PWM support Alistair Francis
2021-09-21  6:54 ` [PULL v2 09/21] sifive_u: Connect the SiFive PWM device Alistair Francis
2021-09-21  6:54 ` [PULL v2 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources Alistair Francis
2021-09-21  6:54 ` [PULL v2 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Alistair Francis
2021-09-21  6:54 ` [PULL v2 12/21] hw/riscv: virt: Re-factor FDT generation Alistair Francis
2021-09-21  6:54 ` [PULL v2 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine Alistair Francis
2021-09-21  6:54 ` [PULL v2 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set Alistair Francis
2021-09-21  6:54 ` [PULL v2 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions Alistair Francis
2021-09-21  6:54 ` [PULL v2 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions Alistair Francis
2021-09-21  6:54 ` [PULL v2 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer Alistair Francis
2021-09-21  6:54 ` [PULL v2 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions Alistair Francis
2021-09-21  6:54 ` [PULL v2 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped Alistair Francis
2021-09-21  6:54 ` Alistair Francis [this message]
2021-09-21  6:54 ` [PULL v2 21/21] hw/riscv: opentitan: Correct the USB Dev address Alistair Francis
2021-09-21 20:49 ` [PULL v2 00/21] riscv-to-apply queue Richard Henderson

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