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From: Boris Brezillon <boris.brezillon@collabora.com>
To: Joerg Roedel <joro@8bytes.org>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	Tomeu Vizoso <tomeu.vizoso@collabora.com>,
	Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>,
	Steven Price <steven.price@arm.com>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Cc: Boris Brezillon <boris.brezillon@collabora.com>,
	dri-devel@lists.freedesktop.org
Subject: [PATCH v2 2/5] [RFC]iommu/io-pgtable-arm: Take the DEVONLY flag into account on ARM_MALI_LPAE
Date: Fri,  1 Oct 2021 16:34:24 +0200	[thread overview]
Message-ID: <20211001143427.1564786-3-boris.brezillon@collabora.com> (raw)
In-Reply-To: <20211001143427.1564786-1-boris.brezillon@collabora.com>

Restrict the shareability domain when mapping buffers that are
GPU-visible only.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
Flagged RFC because I'm not sure adding a new flag is the right
way to convey the 'dev-private buffer' information.
---
 drivers/iommu/io-pgtable-arm.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index dd9e47189d0d..6ac3defb9ae1 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -450,16 +450,25 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
 				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
 	}
 
-	/*
-	 * Also Mali has its own notions of shareability wherein its Inner
-	 * domain covers the cores within the GPU, and its Outer domain is
-	 * "outside the GPU" (i.e. either the Inner or System domain in CPU
-	 * terms, depending on coherency).
-	 */
-	if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
+	if (data->iop.fmt == ARM_MALI_LPAE) {
+		/*
+		 * Mali has its own notions of shareability wherein its Inner
+		 * domain covers the cores within the GPU, and its Outer domain
+		 * is "outside the GPU" (i.e. either the Inner or System domain
+		 * in CPU terms, depending on coherency).
+		 * If the mapping is only device-visible, we can use the Inner
+		 * domain, otherwise we need to stick to Outer domain
+		 * shareability.
+		 */
+		if (prot & IOMMU_DEVONLY)
+			pte |= ARM_LPAE_PTE_SH_IS;
+		else
+			pte |= ARM_LPAE_PTE_SH_OS;
+	} else if (prot & IOMMU_CACHE) {
 		pte |= ARM_LPAE_PTE_SH_IS;
-	else
+	} else {
 		pte |= ARM_LPAE_PTE_SH_OS;
+	}
 
 	if (prot & IOMMU_NOEXEC)
 		pte |= ARM_LPAE_PTE_XN;
-- 
2.31.1

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: Joerg Roedel <joro@8bytes.org>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	Tomeu Vizoso <tomeu.vizoso@collabora.com>,
	Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>,
	Steven Price <steven.price@arm.com>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Cc: dri-devel@lists.freedesktop.org,
	Boris Brezillon <boris.brezillon@collabora.com>
Subject: [PATCH v2 2/5] [RFC]iommu/io-pgtable-arm: Take the DEVONLY flag into account on ARM_MALI_LPAE
Date: Fri,  1 Oct 2021 16:34:24 +0200	[thread overview]
Message-ID: <20211001143427.1564786-3-boris.brezillon@collabora.com> (raw)
In-Reply-To: <20211001143427.1564786-1-boris.brezillon@collabora.com>

Restrict the shareability domain when mapping buffers that are
GPU-visible only.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
Flagged RFC because I'm not sure adding a new flag is the right
way to convey the 'dev-private buffer' information.
---
 drivers/iommu/io-pgtable-arm.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index dd9e47189d0d..6ac3defb9ae1 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -450,16 +450,25 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
 				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
 	}
 
-	/*
-	 * Also Mali has its own notions of shareability wherein its Inner
-	 * domain covers the cores within the GPU, and its Outer domain is
-	 * "outside the GPU" (i.e. either the Inner or System domain in CPU
-	 * terms, depending on coherency).
-	 */
-	if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
+	if (data->iop.fmt == ARM_MALI_LPAE) {
+		/*
+		 * Mali has its own notions of shareability wherein its Inner
+		 * domain covers the cores within the GPU, and its Outer domain
+		 * is "outside the GPU" (i.e. either the Inner or System domain
+		 * in CPU terms, depending on coherency).
+		 * If the mapping is only device-visible, we can use the Inner
+		 * domain, otherwise we need to stick to Outer domain
+		 * shareability.
+		 */
+		if (prot & IOMMU_DEVONLY)
+			pte |= ARM_LPAE_PTE_SH_IS;
+		else
+			pte |= ARM_LPAE_PTE_SH_OS;
+	} else if (prot & IOMMU_CACHE) {
 		pte |= ARM_LPAE_PTE_SH_IS;
-	else
+	} else {
 		pte |= ARM_LPAE_PTE_SH_OS;
+	}
 
 	if (prot & IOMMU_NOEXEC)
 		pte |= ARM_LPAE_PTE_XN;
-- 
2.31.1


WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: Joerg Roedel <joro@8bytes.org>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	Tomeu Vizoso <tomeu.vizoso@collabora.com>,
	Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>,
	Steven Price <steven.price@arm.com>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Cc: dri-devel@lists.freedesktop.org,
	Boris Brezillon <boris.brezillon@collabora.com>
Subject: [PATCH v2 2/5] [RFC]iommu/io-pgtable-arm: Take the DEVONLY flag into account on ARM_MALI_LPAE
Date: Fri,  1 Oct 2021 16:34:24 +0200	[thread overview]
Message-ID: <20211001143427.1564786-3-boris.brezillon@collabora.com> (raw)
In-Reply-To: <20211001143427.1564786-1-boris.brezillon@collabora.com>

Restrict the shareability domain when mapping buffers that are
GPU-visible only.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
Flagged RFC because I'm not sure adding a new flag is the right
way to convey the 'dev-private buffer' information.
---
 drivers/iommu/io-pgtable-arm.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index dd9e47189d0d..6ac3defb9ae1 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -450,16 +450,25 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
 				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
 	}
 
-	/*
-	 * Also Mali has its own notions of shareability wherein its Inner
-	 * domain covers the cores within the GPU, and its Outer domain is
-	 * "outside the GPU" (i.e. either the Inner or System domain in CPU
-	 * terms, depending on coherency).
-	 */
-	if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
+	if (data->iop.fmt == ARM_MALI_LPAE) {
+		/*
+		 * Mali has its own notions of shareability wherein its Inner
+		 * domain covers the cores within the GPU, and its Outer domain
+		 * is "outside the GPU" (i.e. either the Inner or System domain
+		 * in CPU terms, depending on coherency).
+		 * If the mapping is only device-visible, we can use the Inner
+		 * domain, otherwise we need to stick to Outer domain
+		 * shareability.
+		 */
+		if (prot & IOMMU_DEVONLY)
+			pte |= ARM_LPAE_PTE_SH_IS;
+		else
+			pte |= ARM_LPAE_PTE_SH_OS;
+	} else if (prot & IOMMU_CACHE) {
 		pte |= ARM_LPAE_PTE_SH_IS;
-	else
+	} else {
 		pte |= ARM_LPAE_PTE_SH_OS;
+	}
 
 	if (prot & IOMMU_NOEXEC)
 		pte |= ARM_LPAE_PTE_XN;
-- 
2.31.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-10-01 14:34 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-01 14:34 [PATCH v2 0/5] drm/panfrost: Add extra GPU-usage flags Boris Brezillon
2021-10-01 14:34 ` Boris Brezillon
2021-10-01 14:34 ` Boris Brezillon
2021-10-01 14:34 ` [PATCH v2 1/5] [RFC]iommu: Add a IOMMU_DEVONLY protection flag Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon
2021-10-01 17:31   ` Alyssa Rosenzweig
2021-10-01 17:31     ` Alyssa Rosenzweig
2021-10-01 17:31     ` Alyssa Rosenzweig
2021-10-18 10:25   ` Joerg Roedel
2021-10-18 10:25     ` Joerg Roedel
2021-10-18 10:25     ` Joerg Roedel
2021-10-18 12:03     ` Boris Brezillon
2021-10-18 12:03       ` Boris Brezillon
2021-10-18 12:03       ` Boris Brezillon
2021-10-01 14:34 ` Boris Brezillon [this message]
2021-10-01 14:34   ` [PATCH v2 2/5] [RFC]iommu/io-pgtable-arm: Take the DEVONLY flag into account on ARM_MALI_LPAE Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon
2021-10-01 14:34 ` [PATCH v2 3/5] drm/panfrost: Add PANFROST_BO_NO{READ,WRITE} flags Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon
2021-10-01 14:36   ` Boris Brezillon
2021-10-01 14:36     ` Boris Brezillon
2021-10-01 14:36     ` Boris Brezillon
2021-10-01 14:34 ` [PATCH v2 4/5] drm/panfrost: Add a PANFROST_BO_GPUONLY flag Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon
2021-10-01 15:13   ` Steven Price
2021-10-01 15:13     ` Steven Price
2021-10-01 15:13     ` Steven Price
2021-10-01 16:22     ` Boris Brezillon
2021-10-01 16:22       ` Boris Brezillon
2021-10-01 16:22       ` Boris Brezillon
2021-10-01 17:30       ` Alyssa Rosenzweig
2021-10-01 17:30         ` Alyssa Rosenzweig
2021-10-01 17:30         ` Alyssa Rosenzweig
2021-10-01 14:34 ` [PATCH v2 5/5] drm/panfrost: Bump the driver version to 1.3 Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon
2021-10-01 14:34   ` Boris Brezillon

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