From: Suzuki K Poulose <suzuki.poulose@arm.com> To: will@kernel.org, mathieu.poirier@linaro.org Cc: catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v4 05/15] coresight: trbe: Add a helper to calculate the trace generated Date: Tue, 12 Oct 2021 14:17:33 +0100 [thread overview] Message-ID: <20211012131743.2040596-6-suzuki.poulose@arm.com> (raw) In-Reply-To: <20211012131743.2040596-1-suzuki.poulose@arm.com> We collect the trace from the TRBE on FILL event from IRQ context and via update_buffer(), when the event is stopped. Let us consolidate how we calculate the trace generated into a helper. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- Changes since v2: - Fix code style issues - Read base pointer directly now. Switch to using cached value of the base of the ring buffer, when this changes. --- drivers/hwtracing/coresight/coresight-trbe.c | 47 ++++++++++++-------- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 2825ccb0cf39..5902ef41bfb8 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -499,6 +499,29 @@ static enum trbe_fault_action trbe_get_fault_act(u64 trbsr) return TRBE_FAULT_ACT_SPURIOUS; } +static unsigned long trbe_get_trace_size(struct perf_output_handle *handle, + struct trbe_buf *buf, bool wrap) +{ + u64 write; + u64 start_off, end_off; + + /* + * If the TRBE has wrapped around the write pointer has + * wrapped and should be treated as limit. + */ + if (wrap) + write = get_trbe_limit_pointer(); + else + write = get_trbe_write_pointer(); + + end_off = write - get_trbe_base_pointer(); + start_off = PERF_IDX2OFF(handle->head, buf); + + if (WARN_ON_ONCE(end_off < start_off)) + return 0; + return (end_off - start_off); +} + static void *arm_trbe_alloc_buffer(struct coresight_device *csdev, struct perf_event *event, void **pages, int nr_pages, bool snapshot) @@ -560,9 +583,9 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev, struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); struct trbe_buf *buf = config; enum trbe_fault_action act; - unsigned long size, offset; - unsigned long write, base, status; + unsigned long size, status; unsigned long flags; + bool wrap = false; WARN_ON(buf->cpudata != cpudata); WARN_ON(cpudata->cpu != smp_processor_id()); @@ -602,8 +625,6 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev, * handle gets freed in etm_event_stop(). */ trbe_drain_and_disable_local(); - write = get_trbe_write_pointer(); - base = get_trbe_base_pointer(); /* Check if there is a pending interrupt and handle it here */ status = read_sysreg_s(SYS_TRBSR_EL1); @@ -627,20 +648,11 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev, goto done; } - /* - * Otherwise, the buffer is full and the write pointer - * has reached base. Adjust this back to the Limit pointer - * for correct size. Also, mark the buffer truncated. - */ - write = get_trbe_limit_pointer(); trbe_report_wrap_event(handle); + wrap = true; } - offset = write - base; - if (WARN_ON_ONCE(offset < PERF_IDX2OFF(handle->head, buf))) - size = 0; - else - size = offset - PERF_IDX2OFF(handle->head, buf); + size = trbe_get_trace_size(handle, buf, wrap); done: local_irq_restore(flags); @@ -721,11 +733,10 @@ static int trbe_handle_overflow(struct perf_output_handle *handle) { struct perf_event *event = handle->event; struct trbe_buf *buf = etm_perf_sink_config(handle); - unsigned long offset, size; + unsigned long size; struct etm_event_data *event_data; - offset = get_trbe_limit_pointer() - get_trbe_base_pointer(); - size = offset - PERF_IDX2OFF(handle->head, buf); + size = trbe_get_trace_size(handle, buf, true); if (buf->snapshot) handle->head += size; -- 2.25.4
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: will@kernel.org, mathieu.poirier@linaro.org Cc: catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v4 05/15] coresight: trbe: Add a helper to calculate the trace generated Date: Tue, 12 Oct 2021 14:17:33 +0100 [thread overview] Message-ID: <20211012131743.2040596-6-suzuki.poulose@arm.com> (raw) In-Reply-To: <20211012131743.2040596-1-suzuki.poulose@arm.com> We collect the trace from the TRBE on FILL event from IRQ context and via update_buffer(), when the event is stopped. Let us consolidate how we calculate the trace generated into a helper. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- Changes since v2: - Fix code style issues - Read base pointer directly now. Switch to using cached value of the base of the ring buffer, when this changes. --- drivers/hwtracing/coresight/coresight-trbe.c | 47 ++++++++++++-------- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 2825ccb0cf39..5902ef41bfb8 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -499,6 +499,29 @@ static enum trbe_fault_action trbe_get_fault_act(u64 trbsr) return TRBE_FAULT_ACT_SPURIOUS; } +static unsigned long trbe_get_trace_size(struct perf_output_handle *handle, + struct trbe_buf *buf, bool wrap) +{ + u64 write; + u64 start_off, end_off; + + /* + * If the TRBE has wrapped around the write pointer has + * wrapped and should be treated as limit. + */ + if (wrap) + write = get_trbe_limit_pointer(); + else + write = get_trbe_write_pointer(); + + end_off = write - get_trbe_base_pointer(); + start_off = PERF_IDX2OFF(handle->head, buf); + + if (WARN_ON_ONCE(end_off < start_off)) + return 0; + return (end_off - start_off); +} + static void *arm_trbe_alloc_buffer(struct coresight_device *csdev, struct perf_event *event, void **pages, int nr_pages, bool snapshot) @@ -560,9 +583,9 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev, struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); struct trbe_buf *buf = config; enum trbe_fault_action act; - unsigned long size, offset; - unsigned long write, base, status; + unsigned long size, status; unsigned long flags; + bool wrap = false; WARN_ON(buf->cpudata != cpudata); WARN_ON(cpudata->cpu != smp_processor_id()); @@ -602,8 +625,6 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev, * handle gets freed in etm_event_stop(). */ trbe_drain_and_disable_local(); - write = get_trbe_write_pointer(); - base = get_trbe_base_pointer(); /* Check if there is a pending interrupt and handle it here */ status = read_sysreg_s(SYS_TRBSR_EL1); @@ -627,20 +648,11 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev, goto done; } - /* - * Otherwise, the buffer is full and the write pointer - * has reached base. Adjust this back to the Limit pointer - * for correct size. Also, mark the buffer truncated. - */ - write = get_trbe_limit_pointer(); trbe_report_wrap_event(handle); + wrap = true; } - offset = write - base; - if (WARN_ON_ONCE(offset < PERF_IDX2OFF(handle->head, buf))) - size = 0; - else - size = offset - PERF_IDX2OFF(handle->head, buf); + size = trbe_get_trace_size(handle, buf, wrap); done: local_irq_restore(flags); @@ -721,11 +733,10 @@ static int trbe_handle_overflow(struct perf_output_handle *handle) { struct perf_event *event = handle->event; struct trbe_buf *buf = etm_perf_sink_config(handle); - unsigned long offset, size; + unsigned long size; struct etm_event_data *event_data; - offset = get_trbe_limit_pointer() - get_trbe_base_pointer(); - size = offset - PERF_IDX2OFF(handle->head, buf); + size = trbe_get_trace_size(handle, buf, true); if (buf->snapshot) handle->head += size; -- 2.25.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-12 13:18 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-12 13:17 [PATCH v4 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 15:31 ` Randy Dunlap 2021-10-12 15:31 ` Randy Dunlap 2021-10-14 14:17 ` Suzuki K Poulose 2021-10-14 14:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 15:35 ` Randy Dunlap 2021-10-12 15:35 ` Randy Dunlap 2021-10-12 13:17 ` Suzuki K Poulose [this message] 2021-10-12 13:17 ` [PATCH v4 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose 2021-10-12 13:17 ` [PATCH v4 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose 2021-10-12 13:17 ` Suzuki K Poulose
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