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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: will@kernel.org, mathieu.poirier@linaro.org
Cc: catalin.marinas@arm.com, anshuman.khandual@arm.com,
	mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 11/15] coresight: trbe: Add a helper to determine the minimum buffer size
Date: Thu, 14 Oct 2021 23:31:21 +0100	[thread overview]
Message-ID: <20211014223125.2605031-12-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20211014223125.2605031-1-suzuki.poulose@arm.com>

For the TRBE to operate, we need a minimum space available to collect
meaningful trace session. This is currently a few bytes, but we may need
to extend this for working around errata. So, abstract this into a helper
function.

Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-trbe.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index b56b166b2dec..4a50309a892d 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -303,6 +303,11 @@ static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
 	return buf->nr_pages * PAGE_SIZE;
 }
 
+static u64 trbe_min_trace_buf_size(struct perf_output_handle *handle)
+{
+	return TRBE_TRACE_MIN_BUF_SIZE;
+}
+
 /*
  * TRBE Limit Calculation
  *
@@ -473,7 +478,7 @@ static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
 	 * have space for a meaningful run, we rather pad it
 	 * and start fresh.
 	 */
-	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
+	if (limit && ((limit - head) < trbe_min_trace_buf_size(handle))) {
 		trbe_pad_buf(handle, limit - head);
 		limit = __trbe_normal_offset(handle);
 	}
-- 
2.25.4


WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: will@kernel.org, mathieu.poirier@linaro.org
Cc: catalin.marinas@arm.com, anshuman.khandual@arm.com,
	mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 11/15] coresight: trbe: Add a helper to determine the minimum buffer size
Date: Thu, 14 Oct 2021 23:31:21 +0100	[thread overview]
Message-ID: <20211014223125.2605031-12-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20211014223125.2605031-1-suzuki.poulose@arm.com>

For the TRBE to operate, we need a minimum space available to collect
meaningful trace session. This is currently a few bytes, but we may need
to extend this for working around errata. So, abstract this into a helper
function.

Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-trbe.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index b56b166b2dec..4a50309a892d 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -303,6 +303,11 @@ static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
 	return buf->nr_pages * PAGE_SIZE;
 }
 
+static u64 trbe_min_trace_buf_size(struct perf_output_handle *handle)
+{
+	return TRBE_TRACE_MIN_BUF_SIZE;
+}
+
 /*
  * TRBE Limit Calculation
  *
@@ -473,7 +478,7 @@ static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
 	 * have space for a meaningful run, we rather pad it
 	 * and start fresh.
 	 */
-	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
+	if (limit && ((limit - head) < trbe_min_trace_buf_size(handle))) {
 		trbe_pad_buf(handle, limit - head);
 		limit = __trbe_normal_offset(handle);
 	}
-- 
2.25.4


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  parent reply	other threads:[~2021-10-14 22:32 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-14 22:31 [PATCH v5 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19 11:04   ` Will Deacon
2021-10-19 11:04     ` Will Deacon
2021-10-19 11:15     ` Suzuki K Poulose
2021-10-19 11:15       ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19  5:06   ` Anshuman Khandual
2021-10-19  5:06     ` Anshuman Khandual
2021-10-19 11:02   ` Will Deacon
2021-10-19 11:02     ` Will Deacon
2021-10-19 11:36     ` Suzuki K Poulose
2021-10-19 11:36       ` Suzuki K Poulose
2021-10-19 11:42       ` Will Deacon
2021-10-19 11:42         ` Will Deacon
2021-10-19 12:06         ` Suzuki K Poulose
2021-10-19 12:06           ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-18 15:50   ` Mathieu Poirier
2021-10-18 15:50     ` Mathieu Poirier
2021-10-19 13:29     ` Suzuki K Poulose
2021-10-19 13:29       ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19  5:25   ` Anshuman Khandual
2021-10-19  5:25     ` Anshuman Khandual
2021-10-29 10:31   ` Arnd Bergmann
2021-10-29 10:31     ` Arnd Bergmann
2021-10-29 13:00     ` Suzuki K Poulose
2021-10-29 13:00       ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-18 15:51   ` Mathieu Poirier
2021-10-18 15:51     ` Mathieu Poirier
2021-10-18 21:15     ` Suzuki K Poulose
2021-10-18 21:15       ` Suzuki K Poulose
2021-10-19  4:36       ` Anshuman Khandual
2021-10-19  4:36         ` Anshuman Khandual
2021-10-19  8:37         ` Suzuki K Poulose
2021-10-19  8:37           ` Suzuki K Poulose
2021-10-19  5:42   ` Anshuman Khandual
2021-10-19  5:42     ` Anshuman Khandual
2021-10-14 22:31 ` Suzuki K Poulose [this message]
2021-10-14 22:31   ` [PATCH v5 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19  5:55   ` Anshuman Khandual
2021-10-19  5:55     ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19  5:57   ` Anshuman Khandual
2021-10-19  5:57     ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-18 15:54   ` Mathieu Poirier
2021-10-18 15:54     ` Mathieu Poirier
2021-10-19  5:59   ` Anshuman Khandual
2021-10-19  5:59     ` Anshuman Khandual
2021-10-19 10:42   ` Will Deacon
2021-10-19 10:42     ` Will Deacon
2021-10-14 22:31 ` [PATCH v5 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-18 15:54   ` Mathieu Poirier
2021-10-18 15:54     ` Mathieu Poirier
2021-10-19  6:00   ` Anshuman Khandual
2021-10-19  6:00     ` Anshuman Khandual
2021-10-19 10:42   ` Will Deacon
2021-10-19 10:42     ` Will Deacon

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