From: Marc Zyngier <maz@kernel.org> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Lezcano <daniel.lezcano@linaro.org>, Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Peter Shier <pshier@google.com>, Raghavendra Rao Ananta <rananta@google.com>, Ricardo Koller <ricarkol@google.com>, Oliver Upton <oupton@google.com>, Catalin Marinas <catalin.marinas@arm.com>, Linus Walleij <linus.walleij@linaro.org>, kernel-team@android.com Subject: [PATCH v4 17/17] arm64: Add HWCAP for self-synchronising virtual counter Date: Sun, 17 Oct 2021 13:42:25 +0100 [thread overview] Message-ID: <20211017124225.3018098-18-maz@kernel.org> (raw) In-Reply-To: <20211017124225.3018098-1-maz@kernel.org> Since userspace can make use of the CNTVSS_EL0 instruction, expose it via a HWCAP. Suggested-by: Will Deacon <will@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> --- Documentation/arm64/cpu-feature-registers.rst | 12 ++++++++++-- Documentation/arm64/elf_hwcaps.rst | 4 ++++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 3 ++- arch/arm64/kernel/cpuinfo.c | 1 + 6 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index 328e0c454fbd..9f9b8fd06089 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -235,7 +235,15 @@ infrastructure: | DPB | [3-0] | y | +------------------------------+---------+---------+ - 6) ID_AA64MMFR2_EL1 - Memory model feature register 2 + 6) ID_AA64MMFR0_EL1 - Memory model feature register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | ECV | [63-60] | y | + +------------------------------+---------+---------+ + + 7) ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | @@ -243,7 +251,7 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ - 7) ID_AA64ZFR0_EL1 - SVE feature ID register 0 + 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible | diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index ec1a5a63c1d0..af106af8e1c0 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -247,6 +247,10 @@ HWCAP2_MTE Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described by Documentation/arm64/memory-tagging-extension.rst. +HWCAP2_ECV + + Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 8c129db8232a..b100e0055eab 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -105,6 +105,7 @@ #define KERNEL_HWCAP_RNG __khwcap2_feature(RNG) #define KERNEL_HWCAP_BTI __khwcap2_feature(BTI) #define KERNEL_HWCAP_MTE __khwcap2_feature(MTE) +#define KERNEL_HWCAP_ECV __khwcap2_feature(ECV) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index b8f41aa234ee..7b23b16f21ce 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -75,5 +75,6 @@ #define HWCAP2_RNG (1 << 16) #define HWCAP2_BTI (1 << 17) #define HWCAP2_MTE (1 << 18) +#define HWCAP2_ECV (1 << 19) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 26b11ce8fff6..97ed37c6ce5e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -279,7 +279,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), /* @@ -2457,6 +2457,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #ifdef CONFIG_ARM64_MTE HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), #endif /* CONFIG_ARM64_MTE */ + HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 87731fea5e41..6e27b759056a 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -94,6 +94,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_RNG] = "rng", [KERNEL_HWCAP_BTI] = "bti", [KERNEL_HWCAP_MTE] = "mte", + [KERNEL_HWCAP_ECV] = "ecv", }; #ifdef CONFIG_COMPAT -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Lezcano <daniel.lezcano@linaro.org>, Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Peter Shier <pshier@google.com>, Raghavendra Rao Ananta <rananta@google.com>, Ricardo Koller <ricarkol@google.com>, Oliver Upton <oupton@google.com>, Catalin Marinas <catalin.marinas@arm.com>, Linus Walleij <linus.walleij@linaro.org>, kernel-team@android.com Subject: [PATCH v4 17/17] arm64: Add HWCAP for self-synchronising virtual counter Date: Sun, 17 Oct 2021 13:42:25 +0100 [thread overview] Message-ID: <20211017124225.3018098-18-maz@kernel.org> (raw) In-Reply-To: <20211017124225.3018098-1-maz@kernel.org> Since userspace can make use of the CNTVSS_EL0 instruction, expose it via a HWCAP. Suggested-by: Will Deacon <will@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> --- Documentation/arm64/cpu-feature-registers.rst | 12 ++++++++++-- Documentation/arm64/elf_hwcaps.rst | 4 ++++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 3 ++- arch/arm64/kernel/cpuinfo.c | 1 + 6 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index 328e0c454fbd..9f9b8fd06089 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -235,7 +235,15 @@ infrastructure: | DPB | [3-0] | y | +------------------------------+---------+---------+ - 6) ID_AA64MMFR2_EL1 - Memory model feature register 2 + 6) ID_AA64MMFR0_EL1 - Memory model feature register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | ECV | [63-60] | y | + +------------------------------+---------+---------+ + + 7) ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | @@ -243,7 +251,7 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ - 7) ID_AA64ZFR0_EL1 - SVE feature ID register 0 + 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible | diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index ec1a5a63c1d0..af106af8e1c0 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -247,6 +247,10 @@ HWCAP2_MTE Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described by Documentation/arm64/memory-tagging-extension.rst. +HWCAP2_ECV + + Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 8c129db8232a..b100e0055eab 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -105,6 +105,7 @@ #define KERNEL_HWCAP_RNG __khwcap2_feature(RNG) #define KERNEL_HWCAP_BTI __khwcap2_feature(BTI) #define KERNEL_HWCAP_MTE __khwcap2_feature(MTE) +#define KERNEL_HWCAP_ECV __khwcap2_feature(ECV) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index b8f41aa234ee..7b23b16f21ce 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -75,5 +75,6 @@ #define HWCAP2_RNG (1 << 16) #define HWCAP2_BTI (1 << 17) #define HWCAP2_MTE (1 << 18) +#define HWCAP2_ECV (1 << 19) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 26b11ce8fff6..97ed37c6ce5e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -279,7 +279,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), /* @@ -2457,6 +2457,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #ifdef CONFIG_ARM64_MTE HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), #endif /* CONFIG_ARM64_MTE */ + HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 87731fea5e41..6e27b759056a 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -94,6 +94,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_RNG] = "rng", [KERNEL_HWCAP_BTI] = "bti", [KERNEL_HWCAP_MTE] = "mte", + [KERNEL_HWCAP_ECV] = "ecv", }; #ifdef CONFIG_COMPAT -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-17 12:47 UTC|newest] Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-17 12:42 [PATCH v4 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 01/17] clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 02/17] clocksource/arm_arch_timer: Drop CNT*_TVAL read accessors Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 03/17] clocksource/arm_arch_timer: Extend write side of timer register accessors to u64 Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 04/17] clocksource/arm_arch_timer: Move system register timer programming over to CVAL Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 05/17] clocksource/arm_arch_timer: Move drop _tval from erratum function names Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 06/17] clocksource/arm_arch_timer: Fix MMIO base address vs callback ordering issue Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 07/17] clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 08/17] clocksource/arm_arch_timer: Advertise 56bit timer to the core code Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 09/17] clocksource/arm_arch_timer: Work around broken CVAL implementations Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 10/17] clocksource/arm_arch_timer: Remove any trace of the TVAL programming interface Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:40 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 11/17] clocksource/arm_arch_timer: Drop unnecessary ISB on CVAL programming Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:39 ` [tip: timers/core] clocksource/drivers/arm_arch_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 12/17] clocksource/arm_arch_timer: Fix masking for high freq counters Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 13/17] clocksource/arch_arm_timer: Move workaround synchronisation around Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-24 15:39 ` [tip: timers/core] clocksource/drivers/arch_arm_timer: " tip-bot2 for Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 14/17] arm64: Add a capability for FEAT_ECV Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 15/17] arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0 Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 15/17] arm64: Add CNT{P, V}CTSS_EL0 alternatives to cnt{p, v}ct_el0 Marc Zyngier 2021-10-17 12:42 ` [PATCH v4 16/17] arm64: Add handling of CNTVCTSS traps Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier 2021-10-17 12:42 ` Marc Zyngier [this message] 2021-10-17 12:42 ` [PATCH v4 17/17] arm64: Add HWCAP for self-synchronising virtual counter Marc Zyngier 2021-10-19 12:20 ` [PATCH v4 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Will Deacon 2021-10-19 12:20 ` Will Deacon 2021-10-24 15:40 ` [tip: timers/core] Merge branch 'timers/drivers/armv8.6_arch_timer' into timers/drivers/next tip-bot2 for Daniel Lezcano
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