From: Alexey Baturo <baturo.alexey@gmail.com> Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis <alistair.francis@wdc.com>, kupokupokupopo@gmail.com, palmer@dabbelt.com, Bin Meng <bmeng.cn@gmail.com> Subject: [PATCH v14 1/8] [RISCV_PM] Add J-extension into RISC-V Date: Sun, 17 Oct 2021 20:27:21 +0300 [thread overview] Message-ID: <20211017172728.759687-2-space.monkey.delivers@gmail.com> (raw) In-Reply-To: <20211017172728.759687-1-space.monkey.delivers@gmail.com> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..3f28dc5f3a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,6 +67,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -289,6 +290,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb; -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com> Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, kupokupokupopo@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com> Subject: [PATCH v14 1/8] [RISCV_PM] Add J-extension into RISC-V Date: Sun, 17 Oct 2021 20:27:21 +0300 [thread overview] Message-ID: <20211017172728.759687-2-space.monkey.delivers@gmail.com> (raw) In-Reply-To: <20211017172728.759687-1-space.monkey.delivers@gmail.com> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..3f28dc5f3a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,6 +67,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -289,6 +290,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb; -- 2.30.2
next prev parent reply other threads:[~2021-10-17 17:29 UTC|newest] Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-17 17:27 [PATCH v14 0/8] RISC-V Pointer Masking implementation Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo [this message] 2021-10-17 17:27 ` [PATCH v14 1/8] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo 2021-10-17 17:27 ` [PATCH v14 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo 2021-10-17 17:27 ` [PATCH v14 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo 2021-10-19 22:27 ` Alistair Francis 2021-10-17 17:27 ` [PATCH v14 4/8] [RISCV_PM] Add J extension state description Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo 2021-10-19 6:53 ` Alistair Francis 2021-10-19 7:02 ` Alexey Baturo 2021-10-17 17:27 ` [PATCH v14 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo 2021-10-17 17:27 ` [PATCH v14 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo 2021-10-17 17:27 ` [PATCH v14 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo 2021-10-17 17:27 ` [PATCH v14 8/8] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo 2021-10-17 17:27 ` Alexey Baturo
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