From: Hao Wu <wuhaotsh@google.com>
To: peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com,
venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com,
hskinnemoen@google.com
Subject: [PATCH v2 5/7] hw/nvram: Update at24c EEPROM init function in NPCM7xx boards
Date: Thu, 21 Oct 2021 11:39:54 -0700 [thread overview]
Message-ID: <20211021183956.920822-6-wuhaotsh@google.com> (raw)
In-Reply-To: <20211021183956.920822-1-wuhaotsh@google.com>
We made 3 changes to the at24c_eeprom_init function in
npcm7xx_boards.c:
1. We allow the function to take a I2CBus* as parameter. This allows
us to attach an EEPROM device behind an I2C mux which is not
possible with the old method.
2. We make at24c EEPROMs are backed by drives so that we can
specify the content of the EEPROMs.
3. Instead of using i2c address as unit number, This patch assigns
unique unit numbers for each eeproms in each board. This avoids
conflict in providing multiple eeprom contents with the same address.
In the old method if we specify two drives with the same unit number,
the following error will occur: `Device with id 'none85' exists`.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
---
hw/arm/npcm7xx_boards.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index a656169f61..cdb52b9922 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -107,13 +107,18 @@ static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
}
-static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
- uint32_t rsize)
+static void at24c_eeprom_init(I2CBus *i2c_bus, int bus, uint8_t addr,
+ uint32_t rsize, int unit_number)
{
- I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus);
I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
DeviceState *dev = DEVICE(i2c_dev);
+ BlockInterfaceType type = IF_NONE;
+ DriveInfo *dinfo;
+ dinfo = drive_get(type, bus, unit_number);
+ if (dinfo) {
+ qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
+ }
qdev_prop_set_uint32(dev, "rom-size", rsize);
i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
}
@@ -220,8 +225,8 @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
- at24c_eeprom_init(soc, 9, 0x55, 8192);
- at24c_eeprom_init(soc, 10, 0x55, 8192);
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 9, 0x55, 8192, 0);
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 10, 0x55, 8192, 1);
/*
* i2c-11:
--
2.33.0.1079.g6e70778dc9-goog
next prev parent reply other threads:[~2021-10-21 18:46 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 18:39 [PATCH v2 0/7] Misc NPCM7XX patches Hao Wu
2021-10-21 18:39 ` [PATCH v2 1/7] hw/i2c: Clear ACK bit in NPCM7xx SMBus module Hao Wu
2021-11-01 17:35 ` Peter Maydell
2021-10-21 18:39 ` [PATCH v2 2/7] hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus Hao Wu
2021-10-21 18:50 ` Corey Minyard
2021-10-21 18:39 ` [PATCH v2 3/7] hw/adc: Fix CONV bit in NPCM7XX ADC CON register Hao Wu
2021-11-01 17:35 ` Peter Maydell
2021-10-21 18:39 ` [PATCH v2 4/7] hw/adc: Make adci[*] R/W in NPCM7XX ADC Hao Wu
2021-11-01 17:37 ` Peter Maydell
2021-10-21 18:39 ` Hao Wu [this message]
2021-11-01 17:41 ` [PATCH v2 5/7] hw/nvram: Update at24c EEPROM init function in NPCM7xx boards Peter Maydell
2021-11-01 17:47 ` Hao Wu
2021-11-03 9:13 ` Thomas Huth
2021-11-03 21:52 ` Hao Wu
2021-11-04 20:50 ` Peter Maydell
2021-10-21 18:39 ` [PATCH v2 6/7] hw/arm: quanta-gbs-bmc add i2c devices Hao Wu
2021-10-21 18:39 ` [PATCH v2 7/7] hw/arm: Add ID for NPCM7XX SMBus Hao Wu
2021-11-01 17:33 ` Peter Maydell
2021-11-01 22:54 ` Hao Wu
2021-11-02 8:55 ` Philippe Mathieu-Daudé
2021-11-03 10:16 ` Markus Armbruster
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