From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
bmeng.cn@gmail.com, Alistair Francis <Alistair.Francis@wdc.com>
Subject: [PATCH v2 4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function
Date: Fri, 22 Oct 2021 16:01:32 +1000 [thread overview]
Message-ID: <20211022060133.3045020-4-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211022060133.3045020-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 1 -
hw/riscv/microchip_pfsoc.c | 14 +-------------
2 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index d30916f45d..a0673f5f59 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -138,7 +138,6 @@ enum {
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
-#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index e475b6d511..843caabae5 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -187,7 +187,6 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
char *plic_hart_config;
- size_t plic_hart_config_len;
NICInfo *nd;
int i;
@@ -262,18 +261,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
l2lim_mem);
/* create PLIC hart topology configuration string */
- plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
- ms->smp.cpus;
- plic_hart_config = g_malloc0(plic_hart_config_len);
- for (i = 0; i < ms->smp.cpus; i++) {
- if (i != 0) {
- strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
- plic_hart_config_len);
- } else {
- strncat(plic_hart_config, "M", plic_hart_config_len);
- }
- plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
- }
+ plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
/* PLIC */
s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
--
2.31.1
next prev parent reply other threads:[~2021-10-22 6:07 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 6:01 [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-22 6:01 ` [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-22 13:53 ` Bin Meng
2021-10-22 13:53 ` Bin Meng
2021-10-22 6:01 ` [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-22 14:58 ` Bin Meng
2021-10-22 14:58 ` Bin Meng
2021-10-22 6:01 ` Alistair Francis [this message]
2021-10-22 14:58 ` [PATCH v2 4/5] hw/riscv: microchip_pfsoc: " Bin Meng
2021-10-22 14:58 ` Bin Meng
2021-10-22 6:01 ` [PATCH v2 5/5] hw/riscv: virt: " Alistair Francis
2021-10-22 14:58 ` Bin Meng
2021-10-22 14:58 ` Bin Meng
2021-10-22 10:38 ` [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Philippe Mathieu-Daudé
2021-10-22 10:38 ` Philippe Mathieu-Daudé
2021-10-22 13:44 ` Bin Meng
2021-10-22 13:44 ` Bin Meng
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