From: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>, philmd@redhat.com Subject: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions Date: Mon, 25 Oct 2021 14:28:10 +0200 [thread overview] Message-ID: <20211025122818.168890-10-frederic.petrot@univ-grenoble-alpes.fr> (raw) In-Reply-To: <20211025122818.168890-1-frederic.petrot@univ-grenoble-alpes.fr> The 128-bit bitwise instructions do not need any function prototype change as the functions can be applied independently on the lower and upper part of the registers. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> --- target/riscv/translate.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 070db77ca5..b183ad2b6e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -426,7 +426,15 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, func(dest, src1, a->imm); - gen_set_gpr(ctx, a->rd, dest); + if (get_xl(ctx) == MXL_RV128) { + TCGv src1h = get_gprh(ctx, a->rs1); + TCGv desth = dest_gprh(ctx, a->rd); + + func(desth, src1h, -(a->imm < 0)); + gen_set_gpr128(ctx, a->rd, dest, desth); + } else { + gen_set_gpr(ctx, a->rd, dest); + } return true; } @@ -440,7 +448,16 @@ static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext, func(dest, src1, src2); - gen_set_gpr(ctx, a->rd, dest); + if (get_xl(ctx) == MXL_RV128) { + TCGv src1h = get_gprh(ctx, a->rs1); + TCGv src2h = get_gprh(ctx, a->rs2); + TCGv desth = dest_gprh(ctx, a->rd); + + func(desth, src1h, src2h); + gen_set_gpr128(ctx, a->rd, dest, desth); + } else { + gen_set_gpr(ctx, a->rd, dest); + } return true; } -- 2.33.0
WARNING: multiple messages have this Message-ID (diff)
From: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bin.meng@windriver.com, philmd@redhat.com, palmer@dabbelt.com, fabien.portas@grenoble-inp.org, "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr> Subject: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions Date: Mon, 25 Oct 2021 14:28:10 +0200 [thread overview] Message-ID: <20211025122818.168890-10-frederic.petrot@univ-grenoble-alpes.fr> (raw) In-Reply-To: <20211025122818.168890-1-frederic.petrot@univ-grenoble-alpes.fr> The 128-bit bitwise instructions do not need any function prototype change as the functions can be applied independently on the lower and upper part of the registers. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> --- target/riscv/translate.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 070db77ca5..b183ad2b6e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -426,7 +426,15 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, func(dest, src1, a->imm); - gen_set_gpr(ctx, a->rd, dest); + if (get_xl(ctx) == MXL_RV128) { + TCGv src1h = get_gprh(ctx, a->rs1); + TCGv desth = dest_gprh(ctx, a->rd); + + func(desth, src1h, -(a->imm < 0)); + gen_set_gpr128(ctx, a->rd, dest, desth); + } else { + gen_set_gpr(ctx, a->rd, dest); + } return true; } @@ -440,7 +448,16 @@ static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext, func(dest, src1, src2); - gen_set_gpr(ctx, a->rd, dest); + if (get_xl(ctx) == MXL_RV128) { + TCGv src1h = get_gprh(ctx, a->rs1); + TCGv src2h = get_gprh(ctx, a->rs2); + TCGv desth = dest_gprh(ctx, a->rd); + + func(desth, src1h, src2h); + gen_set_gpr128(ctx, a->rd, dest, desth); + } else { + gen_set_gpr(ctx, a->rd, dest); + } return true; } -- 2.33.0
next prev parent reply other threads:[~2021-10-25 12:52 UTC|newest] Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-25 12:28 [PATCH v4 00/17] Adding partial support for 128-bit riscv target Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 12:28 ` [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 20:09 ` Richard Henderson 2021-10-25 20:09 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 15:47 ` Philippe Mathieu-Daudé 2021-10-25 15:47 ` Philippe Mathieu-Daudé 2021-10-25 20:16 ` Richard Henderson 2021-10-25 20:16 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 03/17] target/riscv: additional macros to check instruction support Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-30 23:49 ` Richard Henderson 2021-10-30 23:49 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 15:51 ` Philippe Mathieu-Daudé 2021-10-25 15:51 ` Philippe Mathieu-Daudé 2021-10-25 19:08 ` Richard Henderson 2021-10-25 19:08 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 15:55 ` Philippe Mathieu-Daudé 2021-10-25 15:55 ` Philippe Mathieu-Daudé 2021-10-25 19:10 ` Richard Henderson 2021-10-25 19:10 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-30 23:52 ` Richard Henderson 2021-10-30 23:52 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 07/17] target/riscv: moving some insns close to similar insns Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 15:56 ` Philippe Mathieu-Daudé 2021-10-25 15:56 ` Philippe Mathieu-Daudé 2021-10-25 12:28 ` [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-31 3:41 ` Richard Henderson 2021-10-31 3:41 ` Richard Henderson 2021-10-25 12:28 ` Frédéric Pétrot [this message] 2021-10-25 12:28 ` [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot 2021-10-31 3:44 ` Richard Henderson 2021-10-31 3:44 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-31 3:49 ` Richard Henderson 2021-10-31 3:49 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-31 4:03 ` Richard Henderson 2021-10-31 4:03 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-11-02 12:43 ` Richard Henderson 2021-11-02 12:43 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 13/17] target/riscv: support for 128-bit M extension Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-11-02 13:05 ` Richard Henderson 2021-11-02 13:05 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 14/17] target/riscv: adding high part of some csrs Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 12:28 ` [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 12:28 ` [PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 12:28 ` [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-11-02 13:22 ` Richard Henderson 2021-11-02 13:22 ` Richard Henderson
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