From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: lucas.castro@eldorado.org.br, richard.henderson@linaro.org,
groug@kaod.org, luis.pires@eldorado.org.br,
Matheus Ferst <matheus.ferst@eldorado.org.br>,
david@gibson.dropbear.id.au
Subject: [PATCH v3 09/25] target/ppc: Implement Vector Extract Double to VSR using GPR index insns
Date: Thu, 4 Nov 2021 09:37:03 -0300 [thread overview]
Message-ID: <20211104123719.323713-10-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20211104123719.323713-1-matheus.ferst@eldorado.org.br>
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vextdubvlx: Vector Extract Double Unsigned Byte to VSR using
GPR-specified Left-Index
vextduhvlx: Vector Extract Double Unsigned Halfword to VSR using
GPR-specified Left-Index
vextduwvlx: Vector Extract Double Unsigned Word to VSR using
GPR-specified Left-Index
vextddvlx: Vector Extract Double Doubleword to VSR using
GPR-specified Left-Index
vextdubvrx: Vector Extract Double Unsigned Byte to VSR using
GPR-specified Right-Index
vextduhvrx: Vector Extract Double Unsigned Halfword to VSR using
GPR-specified Right-Index
vextduwvrx: Vector Extract Double Unsigned Word to VSR using
GPR-specified Right-Index
vextddvrx: Vector Extract Double Doubleword to VSR using
GPR-specified Right-Index
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 4 +++
target/ppc/insn32.decode | 12 +++++++++
target/ppc/int_helper.c | 39 +++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.c.inc | 37 +++++++++++++++++++++++++++
4 files changed, 92 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 356495f392..7ff1d055c4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -334,6 +334,10 @@ DEF_HELPER_2(vextuwlx, tl, tl, avr)
DEF_HELPER_2(vextubrx, tl, tl, avr)
DEF_HELPER_2(vextuhrx, tl, tl, avr)
DEF_HELPER_2(vextuwrx, tl, tl, avr)
+DEF_HELPER_5(VEXTDUBVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDUHVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDUWVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDDVLX, void, env, avr, avr, avr, tl)
DEF_HELPER_2(vsbox, void, avr, avr)
DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2eb7fb4e92..e438177b32 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -38,6 +38,9 @@
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+&VA vrt vra vrb rc
+@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
+
&VN vrt vra vrb sh
@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
@@ -347,6 +350,15 @@ VPEXTD 000100 ..... ..... ..... 10110001101 @VX
## Vector Permute and Formatting Instruction
+VEXTDUBVLX 000100 ..... ..... ..... ..... 011000 @VA
+VEXTDUBVRX 000100 ..... ..... ..... ..... 011001 @VA
+VEXTDUHVLX 000100 ..... ..... ..... ..... 011010 @VA
+VEXTDUHVRX 000100 ..... ..... ..... ..... 011011 @VA
+VEXTDUWVLX 000100 ..... ..... ..... ..... 011100 @VA
+VEXTDUWVRX 000100 ..... ..... ..... ..... 011101 @VA
+VEXTDDVLX 000100 ..... ..... ..... ..... 011110 @VA
+VEXTDDVRX 000100 ..... ..... ..... ..... 011111 @VA
+
VINSERTB 000100 ..... - .... ..... 01100001101 @VX_uim4
VINSERTH 000100 ..... - .... ..... 01101001101 @VX_uim4
VINSERTW 000100 ..... - .... ..... 01110001101 @VX_uim4
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 6f9479fd53..b7861776c2 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1642,6 +1642,45 @@ VINSX(D, uint64_t)
#undef ELEM_ADDR
#undef VINSX
#if defined(HOST_WORDS_BIGENDIAN)
+#define VEXTDVLX(NAME, SIZE) \
+void helper_##NAME(CPUPPCState *env, ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ target_ulong index) \
+{ \
+ const target_long idx = index; \
+ ppc_avr_t tmp[2] = { *a, *b }; \
+ memset(t, 0, sizeof(*t)); \
+ if (idx >= 0 && idx + SIZE <= sizeof(tmp)) { \
+ memcpy(&t->u8[ARRAY_SIZE(t->u8) / 2 - SIZE], (void *)tmp + idx, SIZE); \
+ } else { \
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for " #NAME " after 0x" \
+ TARGET_FMT_lx ", RC = " TARGET_FMT_ld " > %d\n", \
+ env->nip, idx < 0 ? SIZE - idx : idx, 32 - SIZE); \
+ } \
+}
+#else
+#define VEXTDVLX(NAME, SIZE) \
+void helper_##NAME(CPUPPCState *env, ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ target_ulong index) \
+{ \
+ const target_long idx = index; \
+ ppc_avr_t tmp[2] = { *b, *a }; \
+ memset(t, 0, sizeof(*t)); \
+ if (idx >= 0 && idx + SIZE <= sizeof(tmp)) { \
+ memcpy(&t->u8[ARRAY_SIZE(t->u8) / 2], \
+ (void *)tmp + sizeof(tmp) - SIZE - idx, SIZE); \
+ } else { \
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for " #NAME " after 0x" \
+ TARGET_FMT_lx ", RC = " TARGET_FMT_ld " > %d\n", \
+ env->nip, idx < 0 ? SIZE - idx : idx, 32 - SIZE); \
+ } \
+}
+#endif
+VEXTDVLX(VEXTDUBVLX, 1)
+VEXTDVLX(VEXTDUHVLX, 2)
+VEXTDVLX(VEXTDUWVLX, 4)
+VEXTDVLX(VEXTDDVLX, 8)
+#undef VEXTDVLX
+#if defined(HOST_WORDS_BIGENDIAN)
#define VEXTRACT(suffix, element) \
void helper_vextract##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
{ \
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 6fd18690df..8eb8d3a067 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1228,6 +1228,43 @@ GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
vextractuw, PPC_NONE, PPC2_ISA300);
+static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
+{
+ TCGv_ptr vrt, vra, vrb;
+ TCGv rc;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ vrt = gen_avr_ptr(a->vrt);
+ vra = gen_avr_ptr(a->vra);
+ vrb = gen_avr_ptr(a->vrb);
+ rc = tcg_temp_new();
+
+ tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F);
+ if (right) {
+ tcg_gen_subfi_tl(rc, 32 - size, rc);
+ }
+ gen_helper(cpu_env, vrt, vra, vrb, rc);
+
+ tcg_temp_free_ptr(vrt);
+ tcg_temp_free_ptr(vra);
+ tcg_temp_free_ptr(vrb);
+ tcg_temp_free(rc);
+ return true;
+}
+
+TRANS(VEXTDUBVLX, do_vextdx, 1, false, gen_helper_VEXTDUBVLX)
+TRANS(VEXTDUHVLX, do_vextdx, 2, false, gen_helper_VEXTDUHVLX)
+TRANS(VEXTDUWVLX, do_vextdx, 4, false, gen_helper_VEXTDUWVLX)
+TRANS(VEXTDDVLX, do_vextdx, 8, false, gen_helper_VEXTDDVLX)
+
+TRANS(VEXTDUBVRX, do_vextdx, 1, true, gen_helper_VEXTDUBVLX)
+TRANS(VEXTDUHVRX, do_vextdx, 2, true, gen_helper_VEXTDUHVLX)
+TRANS(VEXTDUWVRX, do_vextdx, 4, true, gen_helper_VEXTDUWVLX)
+TRANS(VEXTDDVRX, do_vextdx, 8, true, gen_helper_VEXTDDVLX)
+
static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
--
2.25.1
next prev parent reply other threads:[~2021-11-04 13:06 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-04 12:36 [PATCH v3 00/25] PowerISA v3.1 instruction batch matheus.ferst
2021-11-04 12:36 ` [PATCH v3 01/25] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
2021-11-04 12:36 ` [PATCH v3 02/25] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
2021-11-04 12:36 ` [PATCH v3 03/25] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
2021-11-04 12:36 ` [PATCH v3 04/25] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
2021-11-04 12:36 ` [PATCH v3 05/25] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
2021-11-04 17:40 ` Richard Henderson
2021-11-04 12:37 ` [PATCH v3 06/25] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
2021-11-04 12:37 ` [PATCH v3 07/25] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
2021-11-04 12:37 ` [PATCH v3 08/25] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
2021-11-04 12:37 ` matheus.ferst [this message]
2021-11-04 12:37 ` [PATCH v3 10/25] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
2021-11-04 12:37 ` [PATCH v3 11/25] target/ppc: receive high/low as argument in get/set_cpu_vsr matheus.ferst
2021-11-04 12:37 ` [PATCH v3 12/25] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
2021-11-04 12:37 ` [PATCH v3 13/25] target/ppc: moved stxvx and lxvx " matheus.ferst
2021-11-04 12:37 ` [PATCH v3 14/25] target/ppc: added the instructions LXVP and STXVP matheus.ferst
2021-11-04 12:37 ` [PATCH v3 15/25] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
2021-11-04 12:37 ` [PATCH v3 16/25] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
2021-11-04 12:37 ` [PATCH v3 17/25] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
2021-11-04 12:37 ` [PATCH v3 18/25] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
2021-11-04 12:37 ` [PATCH v3 19/25] target/ppc: moved XXSPLTIB " matheus.ferst
2021-11-04 12:37 ` [PATCH v3 20/25] target/ppc: implemented XXSPLTI32DX matheus.ferst
2021-11-04 12:37 ` [PATCH v3 21/25] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
2021-11-04 12:37 ` [PATCH v3 22/25] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
2021-11-04 12:37 ` [PATCH v3 23/25] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
2021-11-04 12:37 ` [PATCH v3 24/25] target/ppc: Implement lxvkq instruction matheus.ferst
2021-11-04 12:37 ` [PATCH v3 25/25] target/ppc: cntlzdm/cnttzdm implementation without brcond matheus.ferst
2021-11-04 17:41 ` Richard Henderson
2021-11-05 1:26 ` [PATCH v3 00/25] PowerISA v3.1 instruction batch David Gibson
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