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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org,
	linux-watchdog@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [RFC 3/4] clk: renesas: r9a07g044: Add WDT clock and reset entries
Date: Thu,  4 Nov 2021 16:08:57 +0000	[thread overview]
Message-ID: <20211104160858.15550-4-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20211104160858.15550-1-biju.das.jz@bp.renesas.com>

Add WDT{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 8618b0f19d7a..79bad86b6cb7 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -146,6 +146,18 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
 				0x52c, 0),
 	DEF_MOD("dmac_pclk",	R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
 				0x52c, 1),
+	DEF_MOD("wdt0_pclk",	R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
+				0x548, 0),
+	DEF_MOD("wdt0_clk",	R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
+				0x548, 1),
+	DEF_MOD("wdt1_pclk",	R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
+				0x548, 2),
+	DEF_MOD("wdt1_clk",	R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
+				0x548, 3),
+	DEF_MOD("wdt2_pclk",	R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
+				0x548, 4),
+	DEF_MOD("wdt2_clk",	R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
+				0x548, 5),
 	DEF_MOD("spi_clk2",	R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
 				0x550, 0),
 	DEF_MOD("spi_clk",	R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
@@ -234,6 +246,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
 	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
 	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
+	DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
+	DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
+	DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
 	DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
 	DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
 	DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
-- 
2.17.1


  parent reply	other threads:[~2021-11-04 16:09 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-04 16:08 [RFC 0/4] Add WDT driver for RZ/G2L Biju Das
2021-11-04 16:08 ` [RFC 1/4] clk: renesas: rzg2l: Add support for watchdog reset selection Biju Das
2021-11-04 16:08 ` [RFC 2/4] dt-bindings: watchdog: renesas,wdt: Add support for RZ/G2L Biju Das
2021-11-08 16:04   ` Geert Uytterhoeven
2021-11-08 16:33     ` Biju Das
2021-11-04 16:08 ` Biju Das [this message]
2021-11-08 16:07   ` [RFC 3/4] clk: renesas: r9a07g044: Add WDT clock and reset entries Geert Uytterhoeven
2021-11-04 16:08 ` [RFC 4/4] watchdog: Add Watchdog Timer driver for RZ/G2L Biju Das
2021-11-08 18:38   ` Guenter Roeck
2021-11-09  8:04     ` Geert Uytterhoeven
2021-11-09  8:22       ` Biju Das
2021-11-09  8:30         ` Geert Uytterhoeven
2021-11-09 10:25     ` Biju Das
2021-11-09  9:56   ` Philipp Zabel
2021-11-09 10:43     ` Biju Das

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