From: guoren@kernel.org To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren <guoren@linux.alibaba.com>, Vincent Pelletier <plr.vincent@gmail.com>, Nikita Shubin <nikita.shubin@maquefel.me>, stable@vger.kernel.org Subject: [PATCH V7] irqchip/sifive-plic: Fixup EOI failed when masked Date: Fri, 5 Nov 2021 17:47:48 +0800 [thread overview] Message-ID: <20211105094748.3894453-1-guoren@kernel.org> (raw) From: Guo Ren <guoren@linux.alibaba.com> When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the driver, only the first interrupt could be handled, and continue irq is blocked by hw. Because the riscv plic couldn't complete masked irq source which has been disabled in enable register. The bug was firstly reported in [1]. Here is the description of Interrupt Completion in PLIC spec [2]: The PLIC signals it has completed executing an interrupt handler by writing the interrupt ID it received from the claim to the claim/complete register. The PLIC does not check whether the completion ID is the same as the last claim ID for that target. If the completion ID does not match an interrupt source that is currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ completion is silently ignored. [1] http://lists.infradead.org/pipermail/linux-riscv/2021-July/007441.html [2] https://github.com/riscv/riscv-plic-spec/blob/8bc15a35d07c9edf7b5d23fec9728302595ffc4d/riscv-plic.adoc Fixes: bb0fed1c60cc ("irqchip/sifive-plic: Switch to fasteoi flow") Reported-by: Vincent Pelletier <plr.vincent@gmail.com> Tested-by: Nikita Shubin <nikita.shubin@maquefel.me> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: stable@vger.kernel.org Cc: Anup Patel <anup@brainfault.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <maz@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Nikita Shubin <nikita.shubin@maquefel.me> Cc: incent Pelletier <plr.vincent@gmail.com> --- Changes since V7: - Add Fixes tag - Add Tested-by - Add Cc stable Changes since V6: - Propagate to plic_irq_eoi for all riscv,plic by Nikita Shubin - Remove thead related codes Changes since V5: - Move back to mask/unmask - Fixup the problem in eoi callback - Remove allwinner,sun20i-d1 IRQCHIP_DECLARE - Rewrite comment log Changes since V4: - Update comment by Anup Changes since V3: - Rename "c9xx" to "c900" - Add sifive_plic_chip and thead_plic_chip for difference Changes since V2: - Add a separate compatible string "thead,c9xx-plic" - set irq_mask/unmask of "plic_chip" to NULL and point irq_enable/disable of "plic_chip" to plic_irq_mask/unmask - Add a detailed comment block in plic_init() about the differences in Claim/Completion process of RISC-V PLIC and C9xx PLIC. --- drivers/irqchip/irq-sifive-plic.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index cf74cfa82045..259065d271ef 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -163,7 +163,13 @@ static void plic_irq_eoi(struct irq_data *d) { struct plic_handler *handler = this_cpu_ptr(&plic_handlers); - writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + if (irqd_irq_masked(d)) { + plic_irq_unmask(d); + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + plic_irq_mask(d); + } else { + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + } } static struct irq_chip plic_chip = { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren <guoren@linux.alibaba.com>, Vincent Pelletier <plr.vincent@gmail.com>, Nikita Shubin <nikita.shubin@maquefel.me>, stable@vger.kernel.org Subject: [PATCH V7] irqchip/sifive-plic: Fixup EOI failed when masked Date: Fri, 5 Nov 2021 17:47:48 +0800 [thread overview] Message-ID: <20211105094748.3894453-1-guoren@kernel.org> (raw) From: Guo Ren <guoren@linux.alibaba.com> When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the driver, only the first interrupt could be handled, and continue irq is blocked by hw. Because the riscv plic couldn't complete masked irq source which has been disabled in enable register. The bug was firstly reported in [1]. Here is the description of Interrupt Completion in PLIC spec [2]: The PLIC signals it has completed executing an interrupt handler by writing the interrupt ID it received from the claim to the claim/complete register. The PLIC does not check whether the completion ID is the same as the last claim ID for that target. If the completion ID does not match an interrupt source that is currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ completion is silently ignored. [1] http://lists.infradead.org/pipermail/linux-riscv/2021-July/007441.html [2] https://github.com/riscv/riscv-plic-spec/blob/8bc15a35d07c9edf7b5d23fec9728302595ffc4d/riscv-plic.adoc Fixes: bb0fed1c60cc ("irqchip/sifive-plic: Switch to fasteoi flow") Reported-by: Vincent Pelletier <plr.vincent@gmail.com> Tested-by: Nikita Shubin <nikita.shubin@maquefel.me> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: stable@vger.kernel.org Cc: Anup Patel <anup@brainfault.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <maz@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Nikita Shubin <nikita.shubin@maquefel.me> Cc: incent Pelletier <plr.vincent@gmail.com> --- Changes since V7: - Add Fixes tag - Add Tested-by - Add Cc stable Changes since V6: - Propagate to plic_irq_eoi for all riscv,plic by Nikita Shubin - Remove thead related codes Changes since V5: - Move back to mask/unmask - Fixup the problem in eoi callback - Remove allwinner,sun20i-d1 IRQCHIP_DECLARE - Rewrite comment log Changes since V4: - Update comment by Anup Changes since V3: - Rename "c9xx" to "c900" - Add sifive_plic_chip and thead_plic_chip for difference Changes since V2: - Add a separate compatible string "thead,c9xx-plic" - set irq_mask/unmask of "plic_chip" to NULL and point irq_enable/disable of "plic_chip" to plic_irq_mask/unmask - Add a detailed comment block in plic_init() about the differences in Claim/Completion process of RISC-V PLIC and C9xx PLIC. --- drivers/irqchip/irq-sifive-plic.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index cf74cfa82045..259065d271ef 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -163,7 +163,13 @@ static void plic_irq_eoi(struct irq_data *d) { struct plic_handler *handler = this_cpu_ptr(&plic_handlers); - writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + if (irqd_irq_masked(d)) { + plic_irq_unmask(d); + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + plic_irq_mask(d); + } else { + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + } } static struct irq_chip plic_chip = { -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2021-11-05 9:48 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-05 9:47 guoren [this message] 2021-11-05 9:47 ` [PATCH V7] irqchip/sifive-plic: Fixup EOI failed when masked guoren 2021-11-06 12:11 ` Aurelien Jarno 2021-11-06 12:11 ` Aurelien Jarno 2021-11-06 13:28 ` Nikita Shubin 2021-11-06 13:28 ` Nikita Shubin 2021-11-06 13:45 ` Anup Patel 2021-11-06 13:45 ` Anup Patel 2021-11-07 13:09 ` Guo Ren 2021-11-07 13:09 ` Guo Ren 2021-11-07 13:13 ` Marc Zyngier 2021-11-07 13:13 ` Marc Zyngier 2021-11-06 14:26 ` [irqchip: irq/irqchip-fixes] " irqchip-bot for Guo Ren 2021-11-12 16:15 ` irqchip-bot for Guo Ren
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