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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org, clg@kaod.org, danielhb413@gmail.com,
	groug@kaod.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Luis Pires" <luis.pires@eldorado.org.br>,
	qemu-ppc@nongnu.org, "David Gibson" <david@gibson.dropbear.id.au>
Subject: [PULL 19/54] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree
Date: Tue,  9 Nov 2021 16:51:29 +1100	[thread overview]
Message-ID: <20211109055204.230765-20-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20211109055204.230765-1-david@gibson.dropbear.id.au>

From: Luis Pires <luis.pires@eldorado.org.br>

Move the following instructions to decodetree:
dtstdc:  DFP Test Data Class
dtstdcq: DFP Test Data Class Quad
dtstdg:  DFP Test Data Group
dtstdgq: DFP Test Data Group Quad

Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-10-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/dfp_helper.c             |  8 +++----
 target/ppc/helper.h                 |  8 +++----
 target/ppc/insn32.decode            | 14 ++++++++++++
 target/ppc/translate/dfp-impl.c.inc | 35 +++++++++++++----------------
 target/ppc/translate/dfp-ops.c.inc  | 10 ---------
 5 files changed, 37 insertions(+), 38 deletions(-)

diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index 6ab46d7db5..f3c1e525a3 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -546,8 +546,8 @@ uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, uint32_t dcm)      \
     return dfp.crbf;                                                     \
 }
 
-DFP_HELPER_TSTDC(dtstdc, 64)
-DFP_HELPER_TSTDC(dtstdcq, 128)
+DFP_HELPER_TSTDC(DTSTDC, 64)
+DFP_HELPER_TSTDC(DTSTDCQ, 128)
 
 #define DFP_HELPER_TSTDG(op, size)                                       \
 uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, uint32_t dcm)      \
@@ -601,8 +601,8 @@ uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, uint32_t dcm)      \
     return dfp.crbf;                                                     \
 }
 
-DFP_HELPER_TSTDG(dtstdg, 64)
-DFP_HELPER_TSTDG(dtstdgq, 128)
+DFP_HELPER_TSTDG(DTSTDG, 64)
+DFP_HELPER_TSTDG(DTSTDGQ, 128)
 
 #define DFP_HELPER_TSTEX(op, size)                                       \
 uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, ppc_fprp_t *b)     \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3812bb0270..2f11411e14 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -710,10 +710,10 @@ DEF_HELPER_3(dcmpo, i32, env, fprp, fprp)
 DEF_HELPER_3(dcmpoq, i32, env, fprp, fprp)
 DEF_HELPER_3(dcmpu, i32, env, fprp, fprp)
 DEF_HELPER_3(dcmpuq, i32, env, fprp, fprp)
-DEF_HELPER_3(dtstdc, i32, env, fprp, i32)
-DEF_HELPER_3(dtstdcq, i32, env, fprp, i32)
-DEF_HELPER_3(dtstdg, i32, env, fprp, i32)
-DEF_HELPER_3(dtstdgq, i32, env, fprp, i32)
+DEF_HELPER_3(DTSTDC, i32, env, fprp, i32)
+DEF_HELPER_3(DTSTDCQ, i32, env, fprp, i32)
+DEF_HELPER_3(DTSTDG, i32, env, fprp, i32)
+DEF_HELPER_3(DTSTDGQ, i32, env, fprp, i32)
 DEF_HELPER_3(dtstex, i32, env, fprp, fprp)
 DEF_HELPER_3(dtstexq, i32, env, fprp, fprp)
 DEF_HELPER_3(dtstsf, i32, env, fprp, fprp)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 33463c14ea..49bdd3531e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -58,6 +58,12 @@
 %x_frbp         12:4 !function=times_2
 @X_vrt_frbp     ...... vrt:5 ..... ....0 .......... .           &X_vrt_frbp frbp=%x_frbp
 
+&Z22_bf_fra     bf fra dm
+@Z22_bf_fra     ...... bf:3 .. fra:5 dm:6 ......... .           &Z22_bf_fra
+
+%z22_frap       17:4 !function=times_2
+@Z22_bf_frap    ...... bf:3 .. ....0 dm:6 ......... .           &Z22_bf_fra fra=%z22_frap
+
 ### Fixed-Point Load Instructions
 
 LBZ             100010 ..... ..... ................     @D
@@ -168,6 +174,14 @@ SETBCR          011111 ..... ..... ----- 0110100000 -   @X_bi
 SETNBC          011111 ..... ..... ----- 0111000000 -   @X_bi
 SETNBCR         011111 ..... ..... ----- 0111100000 -   @X_bi
 
+### Decimal Floating-Point Test Instructions
+
+DTSTDC          111011 ... -- ..... ...... 011000010 -  @Z22_bf_fra
+DTSTDCQ         111111 ... -- ..... ...... 011000010 -  @Z22_bf_frap
+
+DTSTDG          111011 ... -- ..... ...... 011100010 -  @Z22_bf_fra
+DTSTDGQ         111111 ... -- ..... ...... 011100010 -  @Z22_bf_frap
+
 ### Decimal Floating-Point Conversion Instructions
 
 DCFFIXQQ        111111 ..... 00000 ..... 1111100010 -   @X_frtp_vrb
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index 1431d955c6..1a30c51467 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -60,21 +60,17 @@ static void gen_##name(DisasContext *ctx)         \
     tcg_temp_free_ptr(rb);                        \
 }
 
-#define GEN_DFP_BF_A_DCM(name)                    \
-static void gen_##name(DisasContext *ctx)         \
-{                                                 \
-    TCGv_ptr ra;                                  \
-    TCGv_i32 dcm;                                 \
-    if (unlikely(!ctx->fpu_enabled)) {            \
-        gen_exception(ctx, POWERPC_EXCP_FPU);     \
-        return;                                   \
-    }                                             \
-    ra = gen_fprp_ptr(rA(ctx->opcode));           \
-    dcm = tcg_const_i32(DCM(ctx->opcode));        \
-    gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
-                      cpu_env, ra, dcm);          \
-    tcg_temp_free_ptr(ra);                        \
-    tcg_temp_free_i32(dcm);                       \
+#define TRANS_DFP_BF_A_DCM(NAME)                             \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
+{                                                            \
+    TCGv_ptr ra;                                             \
+    REQUIRE_INSNS_FLAGS2(ctx, DFP);                          \
+    REQUIRE_FPU(ctx);                                        \
+    ra = gen_fprp_ptr(a->fra);                               \
+    gen_helper_##NAME(cpu_crf[a->bf],                        \
+                      cpu_env, ra, tcg_constant_i32(a->dm)); \
+    tcg_temp_free_ptr(ra);                                   \
+    return true;                                             \
 }
 
 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2)    \
@@ -174,10 +170,10 @@ GEN_DFP_BF_A_B(dcmpu)
 GEN_DFP_BF_A_B(dcmpuq)
 GEN_DFP_BF_A_B(dcmpo)
 GEN_DFP_BF_A_B(dcmpoq)
-GEN_DFP_BF_A_DCM(dtstdc)
-GEN_DFP_BF_A_DCM(dtstdcq)
-GEN_DFP_BF_A_DCM(dtstdg)
-GEN_DFP_BF_A_DCM(dtstdgq)
+TRANS_DFP_BF_A_DCM(DTSTDC)
+TRANS_DFP_BF_A_DCM(DTSTDCQ)
+TRANS_DFP_BF_A_DCM(DTSTDG)
+TRANS_DFP_BF_A_DCM(DTSTDGQ)
 GEN_DFP_BF_A_B(dtstex)
 GEN_DFP_BF_A_B(dtstexq)
 GEN_DFP_BF_A_B(dtstsf)
@@ -217,7 +213,6 @@ GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
 
 #undef GEN_DFP_T_A_B_Rc
 #undef GEN_DFP_BF_A_B
-#undef GEN_DFP_BF_A_DCM
 #undef GEN_DFP_T_B_U32_U32_Rc
 #undef GEN_DFP_T_A_B_I32_Rc
 #undef GEN_DFP_T_B_Rc
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
index 6ef38e5712..e1df98d52e 100644
--- a/target/ppc/translate/dfp-ops.c.inc
+++ b/target/ppc/translate/dfp-ops.c.inc
@@ -66,12 +66,6 @@ _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
 #define GEN_DFP_BF_A_Bp_300(name, op1, op2)     \
 _GEN_DFP_QUAD_300(name, op1, op2, 0x00400001)
 
-#define GEN_DFP_BF_A_DCM(name, op1, op2) \
-_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
-
-#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
-_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
-
 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
 
@@ -123,10 +117,6 @@ GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
-GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
-GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
-GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
-GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
-- 
2.33.1



  parent reply	other threads:[~2021-11-09  6:31 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-09  5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
2021-11-09  5:51 ` [PULL 01/54] target/ppc: introduce do_ea_calc David Gibson
2021-11-09  5:51 ` [PULL 02/54] target/ppc: move resolve_PLS_D to translate.c David Gibson
2021-11-09  5:51 ` [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree David Gibson
2021-11-10 16:33   ` Laurent Vivier
2021-11-10 16:56     ` Cédric Le Goater
2021-11-10 17:04       ` Laurent Vivier
2021-11-12 13:39         ` Cédric Le Goater
2021-11-09  5:51 ` [PULL 04/54] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions David Gibson
2021-11-09  5:51 ` [PULL 05/54] target/ppc: Move LQ and STQ to decodetree David Gibson
2021-11-09  5:51 ` [PULL 06/54] target/ppc: Implement PLQ and PSTQ David Gibson
2021-11-09  5:51 ` [PULL 07/54] target/ppc: Implement cntlzdm David Gibson
2021-11-09  5:51 ` [PULL 08/54] target/ppc: Implement cnttzdm David Gibson
2021-11-09  5:51 ` [PULL 09/54] target/ppc: Implement pdepd instruction David Gibson
2021-11-09  5:51 ` [PULL 10/54] target/ppc: Implement pextd instruction David Gibson
2021-11-09  5:51 ` [PULL 11/54] libdecnumber: introduce decNumberFrom[U]Int128 David Gibson
2021-11-09  5:51 ` [PULL 12/54] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c David Gibson
2021-11-09  5:51 ` [PULL 13/54] target/ppc: Introduce REQUIRE_FPU David Gibson
2021-11-09  5:51 ` [PULL 14/54] target/ppc: Implement DCFFIXQQ David Gibson
2021-11-09  5:51 ` [PULL 15/54] host-utils: Introduce mulu128 David Gibson
2021-11-09  5:51 ` [PULL 16/54] libdecnumber: Introduce decNumberIntegralToInt128 David Gibson
2021-11-09  5:51 ` [PULL 17/54] target/ppc: Implement DCTFIXQQ David Gibson
2021-11-09  5:51 ` [PULL 18/54] target/ppc: Do not update nip on DFP instructions David Gibson
2021-11-09  5:51 ` David Gibson [this message]
2021-11-09  5:51 ` [PULL 20/54] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree David Gibson
2021-11-09  5:51 ` [PULL 21/54] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] " David Gibson
2021-11-09  5:51 ` [PULL 22/54] target/ppc: Move dquai[q], drint{x,n}[q] " David Gibson
2021-11-09  5:51 ` [PULL 23/54] target/ppc: Move dqua[q], drrnd[q] " David Gibson
2021-11-09  5:51 ` [PULL 24/54] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] " David Gibson
2021-11-09  5:51 ` [PULL 25/54] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] " David Gibson
2021-11-09  5:51 ` [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents David Gibson
2021-11-09  5:51 ` [PULL 27/54] ppc/pegasos2: Suppress warning when qtest enabled David Gibson
2021-11-09  5:51 ` [PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc David Gibson
2021-11-09  5:51 ` [PULL 29/54] target/ppc: Implement vclzdm/vctzdm instructions David Gibson
2021-11-09  5:51 ` [PULL 30/54] target/ppc: Implement vpdepd/vpextd instruction David Gibson
2021-11-09  5:51 ` [PULL 31/54] target/ppc: Implement vsldbi/vsrdbi instructions David Gibson
2021-11-09  5:51 ` [PULL 32/54] target/ppc: Implement Vector Insert from GPR using GPR index insns David Gibson
2021-11-09  5:51 ` [PULL 33/54] target/ppc: Implement Vector Insert Word from GPR using Immediate insns David Gibson
2021-11-09  5:51 ` [PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns David Gibson
2021-11-09  5:51 ` [PULL 35/54] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree David Gibson
2021-11-09  5:51 ` [PULL 36/54] target/ppc: Implement Vector Extract Double to VSR using GPR index insns David Gibson
2021-11-09  5:51 ` [PULL 37/54] target/ppc: Introduce REQUIRE_VSX macro David Gibson
2021-11-09  5:51 ` [PULL 38/54] target/ppc: receive high/low as argument in get/set_cpu_vsr David Gibson
2021-11-09  5:51 ` [PULL 39/54] target/ppc: moved stxv and lxv from legacy to decodtree David Gibson
2021-11-09  5:51 ` [PULL 40/54] target/ppc: moved stxvx and lxvx " David Gibson
2021-11-09  5:51 ` [PULL 41/54] target/ppc: added the instructions LXVP and STXVP David Gibson
2021-11-09  5:51 ` [PULL 42/54] target/ppc: added the instructions LXVPX and STXVPX David Gibson
2021-11-09  5:51 ` [PULL 43/54] target/ppc: added the instructions PLXV and PSTXV David Gibson
2021-11-09  5:51 ` [PULL 44/54] target/ppc: added the instructions PLXVP and PSTXVP David Gibson
2021-11-09  5:51 ` [PULL 45/54] target/ppc: moved XXSPLTW to using decodetree David Gibson
2021-11-09  5:51 ` [PULL 46/54] target/ppc: moved XXSPLTIB " David Gibson
2021-11-09  5:51 ` [PULL 47/54] target/ppc: implemented XXSPLTI32DX David Gibson
2021-11-09  5:51 ` [PULL 48/54] target/ppc: Implemented XXSPLTIW using decodetree David Gibson
2021-11-09  5:51 ` [PULL 49/54] target/ppc: implemented XXSPLTIDP instruction David Gibson
2021-11-09  5:52 ` [PULL 50/54] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions David Gibson
2021-11-09  5:52 ` [PULL 51/54] target/ppc: Implement lxvkq instruction David Gibson
2021-11-09  5:52 ` [PULL 52/54] target/ppc: cntlzdm/cnttzdm implementation without brcond David Gibson
2021-11-09  5:52 ` [PULL 53/54] target/ppc, hw/ppc: Change maintainers David Gibson
2021-11-09  5:52 ` [PULL 54/54] spapr_numa.c: FORM2 table handle nodes with no distance info David Gibson
2021-11-09  8:41 ` [PULL 00/54] ppc-for-6.2 queue 20211109 Richard Henderson

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