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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [PATCH 1/4] drm/i915/dg2: Add Wa_14010547955
Date: Thu, 11 Nov 2021 13:56:41 -0800	[thread overview]
Message-ID: <20211111215644.1123373-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20211111215644.1123373-1-matthew.d.roper@intel.com>

This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver really needs
to do is program a chicken bit to reenable some internal behavior.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++++
 drivers/gpu/drm/i915/i915_reg.h              | 5 +++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0ceee8ac6671..5d50d06f4eb7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -988,6 +988,10 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 	else if (DISPLAY_VER(dev_priv) >= 13)
 		tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 
+	/* Wa_14010547955:dg2 */
+	if (IS_DG2_DISP_STEP(dev_priv, STEP_B0, STEP_FOREVER))
+		tmp |= DG2_RENDER_CCSTAG_4_3_EN;
+
 	intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07d6cf76c389..680ace373e00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8480,8 +8480,9 @@ enum {
 							   _PIPEB_CHICKEN)
 #define   UNDERRUN_RECOVERY_DISABLE_ADLP	REG_BIT(30)
 #define   UNDERRUN_RECOVERY_ENABLE_DG2		REG_BIT(30)
-#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
-#define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
+#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU	REG_BIT(15)
+#define   DG2_RENDER_CCSTAG_4_3_EN		REG_BIT(12)
+#define   PER_PIXEL_ALPHA_BYPASS_EN		REG_BIT(7)
 
 #define FF_MODE2			_MMIO(0x6604)
 #define   FF_MODE2_GS_TIMER_MASK	REG_GENMASK(31, 24)
-- 
2.33.0


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/4] drm/i915/dg2: Add Wa_14010547955
Date: Thu, 11 Nov 2021 13:56:41 -0800	[thread overview]
Message-ID: <20211111215644.1123373-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20211111215644.1123373-1-matthew.d.roper@intel.com>

This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver really needs
to do is program a chicken bit to reenable some internal behavior.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++++
 drivers/gpu/drm/i915/i915_reg.h              | 5 +++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0ceee8ac6671..5d50d06f4eb7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -988,6 +988,10 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 	else if (DISPLAY_VER(dev_priv) >= 13)
 		tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 
+	/* Wa_14010547955:dg2 */
+	if (IS_DG2_DISP_STEP(dev_priv, STEP_B0, STEP_FOREVER))
+		tmp |= DG2_RENDER_CCSTAG_4_3_EN;
+
 	intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07d6cf76c389..680ace373e00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8480,8 +8480,9 @@ enum {
 							   _PIPEB_CHICKEN)
 #define   UNDERRUN_RECOVERY_DISABLE_ADLP	REG_BIT(30)
 #define   UNDERRUN_RECOVERY_ENABLE_DG2		REG_BIT(30)
-#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
-#define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
+#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU	REG_BIT(15)
+#define   DG2_RENDER_CCSTAG_4_3_EN		REG_BIT(12)
+#define   PER_PIXEL_ALPHA_BYPASS_EN		REG_BIT(7)
 
 #define FF_MODE2			_MMIO(0x6604)
 #define   FF_MODE2_GS_TIMER_MASK	REG_GENMASK(31, 24)
-- 
2.33.0


  reply	other threads:[~2021-11-11 21:57 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-11 21:56 [PATCH 0/4] i915: Additional DG2 workarounds Matt Roper
2021-11-11 21:56 ` [Intel-gfx] " Matt Roper
2021-11-11 21:56 ` Matt Roper [this message]
2021-11-11 21:56   ` [Intel-gfx] [PATCH 1/4] drm/i915/dg2: Add Wa_14010547955 Matt Roper
2021-11-12  9:33   ` Jani Nikula
2021-11-11 21:56 ` [PATCH 2/4] drm/i915/dg2: Add Wa_16011777198 Matt Roper
2021-11-11 21:56   ` [Intel-gfx] " Matt Roper
2021-11-11 21:56 ` [PATCH 3/4] drm/i915/dg2: Add Wa_16013000631 Matt Roper
2021-11-11 21:56   ` [Intel-gfx] " Matt Roper
2021-11-12  5:15   ` [Intel-gfx] [PATCH v2 " Matt Roper
2021-11-11 21:56 ` [PATCH 4/4] drm/i915/dg2: extend Wa_1409120013 to DG2 Matt Roper
2021-11-11 21:56   ` [Intel-gfx] " Matt Roper
2021-11-11 22:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Additional DG2 workarounds Patchwork
2021-11-11 22:17 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-11-11 22:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-12  6:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Additional DG2 workarounds (rev2) Patchwork
2021-11-12  6:22 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-11-12  6:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-12  8:30 ` [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Additional DG2 workarounds Patchwork
2021-11-12 13:08 ` [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Additional DG2 workarounds (rev2) Patchwork

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