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From: Nishanth Menon <nm@ti.com>
To: Rob Herring <robh+dt@kernel.org>, Tero Kristo <kristo@kernel.org>,
	Vignesh Raghavendra <vigneshr@ti.com>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Nishanth Menon <nm@ti.com>, <linux-omap@vger.kernel.org>,
	Peng Fan <peng.fan@nxp.com>
Subject: [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets
Date: Fri, 12 Nov 2021 22:36:38 -0600	[thread overview]
Message-ID: <20211113043638.4358-1-nm@ti.com> (raw)

A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 958587d3a33d..64fef4e67d76 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -86,7 +86,7 @@ L2_0: l2-cache0 {
 		cache-level = <2>;
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
-		cache-sets = <2048>;
+		cache-sets = <1024>;
 		next-level-cache = <&msmc_l3>;
 	};
 
-- 
2.32.0


WARNING: multiple messages have this Message-ID (diff)
From: Nishanth Menon <nm@ti.com>
To: Rob Herring <robh+dt@kernel.org>, Tero Kristo <kristo@kernel.org>,
	Vignesh Raghavendra <vigneshr@ti.com>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Nishanth Menon <nm@ti.com>, <linux-omap@vger.kernel.org>,
	Peng Fan <peng.fan@nxp.com>
Subject: [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets
Date: Fri, 12 Nov 2021 22:36:38 -0600	[thread overview]
Message-ID: <20211113043638.4358-1-nm@ti.com> (raw)

A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 958587d3a33d..64fef4e67d76 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -86,7 +86,7 @@ L2_0: l2-cache0 {
 		cache-level = <2>;
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
-		cache-sets = <2048>;
+		cache-sets = <1024>;
 		next-level-cache = <&msmc_l3>;
 	};
 
-- 
2.32.0


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             reply	other threads:[~2021-11-13  4:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-13  4:36 Nishanth Menon [this message]
2021-11-13  4:36 ` [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets Nishanth Menon
2021-12-03 11:07 ` Pratyush Yadav
2021-12-03 11:07   ` Pratyush Yadav
2021-12-06 13:10 ` Vignesh Raghavendra
2021-12-06 13:10   ` Vignesh Raghavendra

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